Table: RPU Registers provides an overview of the RPU system registers. Table 4-4: RPU Registers Register name Description RPU_GLBL_CNTL Global control register for the RPU RPU_GLBL_STATUS Miscellaneous status information for the RPU RPU_ERR_CNTL Error response enable/disable register RPU_RAM Control for extra features of the RAMs RPU_ERR_INJ Reserved RPU_CCF_MASK Common cause signal mask register RPU_INTR_0-4 RPU interrupt injection registers RPU_INTR_MASK_0-4 RPU interrupt injection mask registers RPU_CCF_VAL Common cause signal value register RPU_SAFETY_CHK RPU safety check register RPU_0_CFG Configuration parameters specific to RPU0 RPU_0_STATUS RPU0 status register RPU_0_PWRDWN Power-down request from the Cortex-R5F processors RPU_0_ISR Interrupt status register RPU_0_IMR Interrupt mask register RPU_0_IEN Interrupt enable register RPU_0_IDS Interrupt disable register RPU_0_SLV_BASE Slave base address register RPU_0_AXI_OVER RPU0 AXI override register RPU_1_CFG Configuration parameters specific to RPU1 RPU_1_STATUS RPU1 status register RPU_1_PWRDWN Power-down request from the Cortex-R5F processors RPU_1_ISR Interrupt status register RPU_1_IMR Interrupt mask register RPU_1_IEN Interrupt enable register RPU_1_IDS Interrupt disable register RPU_1_SLV_BASE Slave base address register RPU_1_AXI_OVER RPU1 AXI override register