Serializer and Clock Divider

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

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2.4 English

The serializer and clock divider module are clocked with the high-speed half-rate clocks from the PLL through the PS-GTR transceiver clock and reset distribution block. The parallel data is loaded after the load signal is active. When not being loaded, the data is serially shifted out to the voltage mode driver. The clock divider block, implemented with the serializer, generates all the required clocks for serialization.