The reference clock is generated by the PS clock subsystem using the circuit shown in This Figure. The input clock source can be selected based on the crl_apb.QSPI_REF_CTRL [srcsel] bits, where the source can be from the RPLL, IOPLL, or DPLL. The crl_apb.QSPI_REF_CTRL [divisor0] register selects the 6-bit programmable divider 0. The crl_apb.QSPI_REF_CTRL [divisor1] register selects the 6-bit programmable divider 1. The crl_apb.QSPI_REF_CTRL [clkact] bit selects whether the clock should be gated or enabled.
To generate the Quad-SPI interface clock, the reference clock is divided down by 2, 4, 8, 16, 32, 64, 128, or 256 using the qspi.Config [BAUD_RATE_DIV] bit field. See Answer Record 69831 for how to generate the QSPI interface clock.