Table: Reset System Registers describes the registers that can be used to configure resets belonging to different power domains. Table 38-5: Reset System Registers Register Type Register Name Description Low-Power Domain LPD reset RESET_CTRL Reset control register. Controls miscellaneous functions with regards to triggers. BLOCKONLY_RST Records the reason for the block-only reset. RESET_REASON Records the reason for the reset in the RESET_REASON register. RST_LPD_TOP Software control register for the LPD block. RST_LPD_DBG Debug register for both the LPD and FPD. Only the POR can cause hardware to clear this register. During a debug_reset, the PMU resets this register. RST_LPD_IOU0 Software controlled reset for the GEM. RST_LPD_IOU1 Power-on reset type register. RST_LPD_IOU2 Software control register for the IOU block. Each bit causes a single peripheral or part of the peripheral to be reset. Full-Power Domain FPD reset RST_FPD_TOP FPD block-level software controlled reset. RST_FPD_APU APU block-level software controlled resets.