Table: Reset System Registers describes the registers that can be used to configure resets belonging to different power domains.
Table 38-5: Reset System Registers
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Register Type
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Register Name
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Description
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Low-Power Domain
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LPD reset
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RESET_CTRL
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Reset control register. Controls miscellaneous functions with regards to triggers.
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BLOCKONLY_RST
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Records the reason for the block-only reset.
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RESET_REASON
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Records the reason for the reset in the RESET_REASON register.
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RST_LPD_TOP
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Software control register for the LPD block.
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RST_LPD_DBG
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Debug register for both the LPD and FPD. Only the POR can cause hardware to clear this register. During a debug_reset, the PMU resets this register.
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RST_LPD_IOU0
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Software controlled reset for the GEM.
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RST_LPD_IOU1
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Power-on reset type register.
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RST_LPD_IOU2
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Software control register for the IOU block. Each bit causes a single peripheral or part of the peripheral to be reset.
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Full-Power Domain
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FPD reset
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RST_FPD_TOP
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FPD block-level software controlled reset.
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RST_FPD_APU
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APU block-level software controlled resets.
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