|
Register
|
Bits
|
Name
|
Description
|
Address
|
|
DX0GSR0
|
[15:7]
|
WLPRD
|
Write leveling period: returns the DDR clock period measured by the write leveling LCDL during calibration of byte 0. The measured period is used to generate the control of the write leveling pipeline, which is a function of the write-leveling delay and the clock period. This value is PVT compensated.
|
0xFD0807E0
|
|
DX1GSR0
|
[15:7]
|
WLPRD
|
As described above, but for byte 1.
|
0xFD0808E0
|
|
DX2GSR0
|
[15:7]
|
WLPRD
|
As described above, but for byte 2.
|
0xFD0809E0
|
|
DX3GSR0
|
[15:7]
|
WLPRD
|
As described above, but for byte 3.
|
0xFD080AE0
|
|
DX4GSR0
|
[15:7]
|
WLPRD
|
As described above, but for byte 4.
|
0xFD080BE0
|
|
DX5GSR0
|
[15:7]
|
WLPRD
|
As described above, but for byte 5.
|
0xFD080CE0
|
|
DX6GSR0
|
[15:7]
|
WLPRD
|
As described above, but for byte 6.
|
0xFD080DE0
|
|
DX7GSR0
|
[15:7]
|
WLPRD
|
As described above, but for byte 7.
|
0xFD080EE0
|
|
DX8GSR0
|
[15:7]
|
WLPRD
|
As described above, but for byte 8.
|
0xFD080FE0
|
|
DX0LCDLR0
|
[8:0]
|
WLD
|
Write leveling delay: delay select for the write leveling (WL) LCDL for byte 0.
|
0xFD080780
|
|
DX1LCDLR0
|
[8:0]
|
WLD
|
As described above, but for byte 1.
|
0xFD080880
|
|
DX2LCDLR0
|
[8:0]
|
WLD
|
As described above, but for byte 2.
|
0xFD080980
|
|
DX3LCDLR0
|
[8:0]
|
WLD
|
As described above, but for byte 3.
|
0xFD080A80
|
|
DX4LCDLR0
|
[8:0]
|
WLD
|
As described above, but for byte 4.
|
0xFD080B80
|
|
DX5LCDLR0
|
[8:0]
|
WLD
|
As described above, but for byte 5.
|
0xFD080C80
|
|
DX6LCDLR0
|
[8:0]
|
WLD
|
As described above, but for byte 6.
|
0xFD080D80
|
|
DX7LCDLR0
|
[8:0]
|
WLD
|
As described above, but for byte 7.
|
0xFD080E80
|
|
DX8LCDLR0
|
[8:0]
|
WLD
|
As described above, but for byte 8.
|
0xFD080F80
|
|
DX0LCDLR1
|
[8:0]
|
WDQD
|
Write data delay: delay select for the write data (WDQ) LCDL for byte 0.
|
0xFD080784
|
|
DX1LCDLR1
|
[8:0]
|
WDQD
|
As described above, but for byte 1.
|
0xFD080884
|
|
DX2LCDLR1
|
[8:0]
|
WDQD
|
As described above, but for byte 2.
|
0xFD080984
|
|
DX3LCDLR1
|
[8:0]
|
WDQD
|
As described above, but for byte 3.
|
0xFD080A84
|
|
DX4LCDLR1
|
[8:0]
|
WDQD
|
As described above, but for byte 4.
|
0xFD080B84
|
|
DX5LCDLR1
|
[8:0]
|
WDQD
|
As described above, but for byte 5.
|
0xFD080C84
|
|
DX6LCDLR1
|
[8:0]
|
WDQD
|
As described above, but for byte 6.
|
0xFD080D84
|
|
DX7LCDLR1
|
[8:0]
|
WDQD
|
As described above, but for byte 7.
|
0xFD080E84
|
|
DX8LCDLR1
|
[8:0]
|
WDQD
|
As described above, but for byte 8.
|
0xFD080F84
|
|
DX0GTR0
|
[19:16]
|
WLSL
|
Write leveling system latency: used to adjust the write latency of byte 0 after write leveling.
Valid values:
0000: Write latency = WL-1 DRAM clock period
0001: Write latency = WL-0.5 DRAM clock period
0010: Write latency = WL
0011: Write latency = WL+0.5 DRAM clock period
0100: Write latency = WL+1 DRAM clock period
0101: Write latency = WL+1.5 DRAM clock period
0110: Write latency = WL+2 DRAM clock period
0111: Write latency = WL+2.5 DRAM clock period
1000: Write latency = WL+3 DRAM clock period
1001: Write latency = WL+3.5 DRAM clock period
1010: Write latency = WL + 4 DRAM clock period
1011 - 1111: RESERVED
Write DQS are pipelined according to the table above.
Note: Write data carries additional pipeline delay according to WDQSL.
|
0xFD0807C0
|
|
DX1GTR0
|
[19:16]
|
WLSL
|
As described above, but for byte 1.
|
0xFD0808C0
|
|
DX2GTR0
|
[19:16]
|
WLSL
|
As described above, but for byte 2.
|
0xFD0809C0
|
|
DX3GTR0
|
[19:16]
|
WLSL
|
As described above, but for byte 3.
|
0xFD080AC0
|
|
DX4GTR0
|
[19:16]
|
WLSL
|
As described above, but for byte 4.
|
0xFD080BC0
|
|
DX5GTR0
|
[19:16]
|
WLSL
|
As described above, but for byte 5.
|
0xFD080CC0
|
|
DX6GTR0
|
[19:16]
|
WLSL
|
As described above, but for byte 6.
|
0xFD080DC0
|
|
DX7GTR0
|
[19:16]
|
WLSL
|
As described above, but for byte 7.
|
0xFD080EC0
|
|
DX8GTR0
|
[19:16]
|
WLSL
|
As described above, but for byte 8.
|
0xFD080FC0
|
|
DX0GTR0
|
[26:24]
|
WDQSL
|
DQ write path latency pipeline for byte 0: write data is pipelined by (WLSL + WDQSL). Total write data pipeline is:
[Write leveling system latency] + WDQSL/2 DRAM clock periods.
|
0xFD0807C0
|
|
DX1GTR0
|
[26:24]
|
WDQSL
|
Same as above, for byte 1.
|
0xFD0808C0
|
|
DX2GTR0
|
[26:24]
|
WDQSL
|
Same as above, for byte 2.
|
0xFD0809C0
|
|
DX3GTR0
|
[26:24]
|
WDQSL
|
Same as above, for byte 3.
|
0xFD080AC0
|
|
DX4GTR0
|
[26:24]
|
WDQSL
|
Same as above, for byte 4.
|
0xFD080BC0
|
|
DX5GTR0
|
[26:24]
|
WDQSL
|
Same as above, for byte 5.
|
0xFD080CC0
|
|
DX6GTR0
|
[26:24]
|
WDQSL
|
Same as above, for byte 6.
|
0xFD080DC0
|
|
DX7GTR0
|
[26:24]
|
WDQSL
|
Same as above, for byte 7.
|
0xFD080EC0
|
|
DX8GTR0
|
[26:24]
|
WDQSL
|
Same as above, for byte 8.
|
0xFD080FC0
|