Reset Scheme

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

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2.4 English

The reset scheme of the controller for PCIe is shown in This Figure.

Figure 30-3:      Controller for PCIe Reset Scheme

X-Ref Target - Figure 30-3


Table: Reset Description provides a description of the resets.

Table 30-2:      Reset Description




This is the PCIe protocol reset. In Endpoint mode, this reset is controlled by the host device, and the Endpoint designated MIO pin can be used as an input for this reset. In Root Port mode, this reset is controlled by the software outside the PCIe block, and the MIO pin can be configured as an output to drive the reset.

When the MIO pin is not allocated to the PCIe, this signal is driven High to allow the PCIe block to come out of reset under local software control (pcie_ctrl_rst_n).


This resets the register block that holds the attribute configuration of the controller for PCIe.


The reset pcie_reset_n is controlled by the host. It is possible that this reset is released before the configuration of the PCIe core is completed, thereby causing the controller for PCIe to come out of reset prematurely. This reset allows the software to override the externally controlled pcie_reset_n. Software is required to release this reset only after the integrated block for PCIe attribute programming and the PS-GTR transceiver interface programming is complete.


The AXI interfaces of the AXI-PCIe bridge have a separate clock and reset domain. The reset pcie_bridge_rst_n controls this domain. This reset can be released once the AXI clock domain is stable. This domain does not reset due to a link down to allow the AXI domain (APU or RPU) to (if needed) access the bridge configuration registers.


TIP:   The reset to AXI-PCIe bridge is determined by the mode of operation i.e., whether Root Port or Endpoint as shown in This Figure.