The interrupts from the processing system I/O peripherals (IOP) are routed to the PL. In the other direction, the PL can asynchronously assert 16 interrupts to the PS. These interrupts are assigned a priority level routed to interrupt controllers which aggregate and route them to appropriate processor. Additionally, FIQ/IRQ interrupts are available which are routed directly to the private peripheral interrupt unit of the interrupt controller. Table: PS-PL Interrupts Summary summarizes the interrupts.
|
Type |
Number of Interrupts |
Start ID |
End ID |
Description |
|---|---|---|---|---|
|
PL to PS interrupts |
8 |
89 |
96 |
PL to PS shared peripheral interrupts. |
|
8 |
104 |
111 |
PL to PS shared peripheral interrupts. |
|
|
1 |
29 |
29 |
PL to PS (RPU, APU) inter-processor interrupt. |
|
|
1 |
30 |
30 |
PL to PS (RPU, APU) inter-processor interrupt. |
|
|
1 |
31 |
31 |
PL to PS (RPU, APU) inter-processor interrupt. |
|
|
1 |
32 |
32 |
PL to PS (RPU, APU) inter-processor interrupt. |
|
|
4 |
|
|
PL to APU legacy FIQ |
|
|
4 |
|
|
PL to APU legacy IRQ |
|
|
2 |
|
|
nFIQ (PL to RPU0 and RPU1) |
|
|
2 |
|
|
nIRQ (PL to RPU0 and RPU1) |
|
|
PS to PL interrupt outputs |
100 |
~ |
~ |
Interrupts generated by I/O peripherals in the LPD and distributed to the GICs and PL. See This Figure(1). |
|
64 |
~ |
~ |
Interrupts generated by I/O peripherals in the FPD and distributed to the GICs and PL. See This Figure(1). |
|
|
Notes: 1.The interrupts generated from the I/O peripherals are distributed to GIC and PL and can only be routed to either GIC or to PL, but not both at the same time. |
||||
For more information on interrupts, refer to Interrupts.