MIO Signals

Zynq UltraScale+ Device Technical Reference Manual (UG1085)
Document ID
UG1085
Release Date
2023-12-21
Revision
2.4 English

The PCIe Root Port mode and Endpoint mode reset signals are routed to specific MIO pins as listed in Table: PCIe Reset Signals on MIO.

Table 30-10:      PCIe Reset Signals on MIO

PCIe Reset

MIO Pins

I/O

Default Input Value to Controller

Rootport reset output (use GPIO controller)

0  ... 77

O

~

Endpoint reset input

29,30,31,33,34,35,36,37

I

0