PS Instances

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID

UG1085

Release Date

2023-12-21

Revision

2.4 English

There are four APM units in on the PS AXI interconnect and are characterized in Table: APM Units. Each APM has one slot as listed in Table: APM Units, except the DDR_APM has six slots corresponding to the six DDR memory controller ports.

Table 15-2: APM Units
Unit Name	Number of Counters	Power Domain	Clock	Register Set	Location
DDR_APM	10	FPD	TOPSW_LSBUS_CLK	APM_DDR	Six AMD AXI port interface (XPI) data ports on the DDR memory controller.
CCI_APM	8	FPD	TOPSW_LSBUS_CLK	APM_CCI_INTC	AXI channel from the CCI to the main switch.
OCM_APM	8	LPD	LPD_LSBUS_CLK	APM_INTC_OCM	AXI channel from the OCM switch to the OCM memory.
LPD_APM	8	LPD	LPD_LSBUS_CLK	APM_LPD_FPD	AXI channel from the LPD switch to the FPD main switch.

The following table shows which PS clock increments the Global Clock Count Register for each instance of the APM.

Table 15-3: GCCR Clock per APM Instance
Unit Name	GCCR Clock
DDR_APM	DDR_REF_CLK
CCI_APM	DDR_REF_CLK
OCM_APM	CPU_R5_CLK
LPD_APM	LPD_SWITCH_CLK