|
Task
|
SD{0, 1}
Registers
|
Register Field
|
Register Offset
|
Bits
|
Value
|
|
Check the command inhibit to make sure no other command transfer is in progress.
|
reg_presentstate
|
presentstate_inhibitcmd
|
0x24
|
0
|
Read
|
|
Write block count register.
|
reg_blockcount
|
xfer_blockcount
|
0x06
|
15:0
|
Block count
|
|
Write timeout.
|
reg_timeoutcontrol
|
timeout_ctrvalue
|
0x2E
|
3:0
|
0x0E
|
|
Write argument register.
|
reg_argument1lo
|
command_argument1
|
0x08
|
15:0
|
Argument
|
|
Clear all normal status interrupts.
|
reg_normalintrsts
|
ALL
|
0x30
|
15:0
|
0xFFFF
|
|
Clear all error status interrupts.
|
reg_errorintrsts
|
All
|
0x36
|
12:0
|
0xF3FF
|
|
Frame the command.
|
|
Check for data inhibit in case of command using DAT lines.
|
reg_presentstate
|
presentstate_inhibitdat
|
0x24
|
1
|
Read
|
|
Write command.
|
reg_command
|
ALL
|
0x0E
|
13:0
|
Command
|
|
Polling for response while command complete bit set.
|
reg_normalintrsts
|
normalintrsts_cmdcomplete
|
0x30
|
0
|
Read until set
|
|
Clear error bits if error interrupt bit sets from previous operation.
|
reg_errorintrsts
|
ALL
|
0x32
|
15:0
|
0xF3FF
|
|
Clear command complete bit.
|
reg_normalintrsts
|
normalintrsts_cmdcomplete
|
0x30
|
0
|
1b'1
|