The PS interconnect assigns the master ID bits and transfers these bits on the AxUSER bits of the associated AXI transaction. For masters that support multiple channels or sources, a portion of the master ID bits are derived from the AXI ID (AWID/ARID) of the associated AXI transaction. This allows the user to enforce system-level protection on a per channel, per processor, or per PL IP basis. In the context of the SMMU, the description of a master ID and a stream ID have the same meaning.
Note: The PS interconnect assigns the master ID bits and transfers these bits on the AxUSER bits of the associated AXI transaction.
Table 16-13: Master IDs List
|
Master Device
|
Master ID [9:0]
|
|
RPU0
|
0000, 00, AXI ID[3:0]
|
|
RPU1
|
0000, 01, AXI ID[3:0]
|
|
PMU processor
|
0001, 00, 0000
|
|
CSU processor
|
0001, 01, 0000
|
|
CSU DMA
|
0001, 01, 0001
|
|
USB0
|
0001, 10, 0000
|
|
USB1
|
0001, 10, 0001
|
|
DAP APB control
|
0001, 10, 0010
|
|
LPD DMA
|
0001, 10, 1xxx CH{0:7}
|
|
SD0
|
0001, 11, 0000
|
|
SD1
|
0001, 11, 0001
|
|
NAND
|
0001, 11, 0010
|
|
QSPI
|
0001, 11, 0011
|
|
GEM0
|
0001, 11, 0100
|
|
GEM1
|
0001, 11, 0101
|
|
GEM2
|
0001, 11, 0110
|
|
GEM3
|
0001, 11, 0111
|
|
SMMU TCU
|
0000, 00, 0000
|
|
CCI-400
|
0000, 00, 0000
|
|
APU
|
APU 0010, AXI ID [5:0]
|
|
SATA
|
0011, 00, 000x DMA{0, 1}
|
|
GPU
|
0011, 00, 0100
|
|
DAP AXI CoreSight
|
0011, 00, 0101
|
|
PCIe
|
0011, 01, 0000
|
|
DisplayPort DMA
|
0011, 10, 0xxx DMA{0:5}
|
|
FPD DMA
|
0011, 10, 1xxx CH{0:7}
|
|
S_AXI_HPC0_FPD (HPC0)
|
1000, AXI ID [5:0] from PL
|
|
S_AXI_HPC1_FPD (HPC1)
|
1001, AXI ID [5:0] from PL
|
|
S_AXI_HP0_FPD (HP0)
|
1010, AXI ID [5:0] from PL
|
|
S_AXI_HP1_FPD (HP1)
|
1011, AXI ID [5:0] from PL
|
|
S_AXI_HP2_FPD (HP2)
|
1100, AXI ID [5:0] from PL
|
|
S_AXI_HP3_FPD (HP3)
|
1101, AXI ID [5:0] from PL
|
|
S_AXI_LPD (PL_LPD)
|
1110, AXI ID [5:0] from PL
|
|
S_AXI_ACE_FPD (ACE)
|
1111, AXI ID [5:0] from PL
|
|
Notes:
1.Each R5 CPU can be identified by its Master ID. However, there is only one Master ID for the A53 cluster of CPUs.
|