The CoreSight TPIU data output signals are independently routed to the MIO using the IOU_SLCR.MIO_PIN_xx registers. Unrouted signals default to the EMIO interface. The TPIU output interface signals are listed in Table: CoreSight TPIU I/O Interfaces.
The MIO pins are described in the Multiplexed I/O. The EMIO signals are described in the Zynq UltraScale+ MPSoC Processing System: LogiCORE IP Product Guide PG201 [Ref 5].
|
MIO |
EMIO |
||||
|---|---|---|---|---|---|
|
Signal Name |
Index(1) |
Pin |
I/O |
Signal Name |
I/O |
|
dbg_trace_clk |
0 |
0, 38, 52 |
O |
pl_ps_trace_clk |
I |
|
dbg_ctl |
1 |
1, 39, 53 |
O |
ps_pl_tracectl |
O |
|
DQ[0] |
2 |
2, 40, 54 |
O |
ps_pl_tracedata[0] |
O |
|
DQ [1] |
3 |
3, 41, 55 |
O |
ps_pl_tracedata[1] |
O |
|
DQ [2] |
4 |
4, 42, 56 |
O |
ps_pl_tracedata[2] |
O |
|
DQ [3] |
5 |
5, 43, 57 |
O |
ps_pl_tracedata[3] |
O |
|
DQ [4] |
6 |
6, 26, 58 |
O |
ps_pl_tracedata[4] |
O |
|
DQ [5] |
7 |
7, 27, 59 |
O |
ps_pl_tracedata[5] |
O |
|
DQ [6] |
8 |
8, 28, 60 |
O |
ps_pl_tracedata[6] |
O |
|
DQ [7] |
9 |
9, 29, 61 |
O |
ps_pl_tracedata[7] |
O |
|
DQ [8] |
10 |
10, 30, 62 |
O |
ps_pl_tracedata[8] |
O |
|
DQ [9] |
11 |
11, 31, 63 |
O |
ps_pl_tracedata[9] |
O |
|
DQ [10] |
12 |
12, 32, 64 |
O |
ps_pl_tracedata[10] |
O |
|
DQ [11] |
13 |
13, 33, 65 |
O |
ps_pl_tracedata[11] |
O |
|
DQ [12] |
14 |
14, 34, 66 |
O |
ps_pl_tracedata[12] |
O |
|
DQ [13] |
15 |
15, 35, 67 |
O |
ps_pl_tracedata[13] |
O |
|
DQ [14] |
16 |
16, 36, 68 |
O |
ps_pl_tracedata[14] |
O |
|
DQ [15] |
17 |
17, 37, 69 |
O |
ps_pl_tracedata[15] |
O |
|
~ |
~ |
~ |
~ |
ps_pl_tracedata[16:31] |
O |
|
Notes: 1.The index numbers are shown in Table: MIO Interfaces. |
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