The RPU MPCore reference clock reference is based on the basic clock generator design with one divider and two clock enables. The extra clock enable is for the subsystem.
The clock gating behavior of the RPU clock is controlled by the clock and reset module in the low power domain region. When the clock and reset module turns the clock gate enable on, the RPU and its GIC receive the clock. When clock gating is turned off, the entire RPU subsystem is not clocked.