1.Set the direction of transfer as write and clear the FIFOs. Write 40h to the Control register. 2.Clear the interrupts. Read and write back the read value to the ISR status register. 3.Enable the timeout, NACK, TX overflow, arbitration lost, DATA, and completion interrupts. Write 24Fh to the IER interrupt enable register. 4.Enable the bus hold logic. Set Control [HOLD] bit if the write data count is greater than the FIFO depth. 5.Calculate the space available in the FIFO. Subtract the Transfer_Size register value from the FIFO depth. 6.Fill the data into the FIFO. Write the data to the Data register based on the count obtained in step 5. 7.Write the slave address. Write the address to the Address register. 8.Wait for the data to be sent. Check that the ISR [COMP] bit is set. a.If writing further data, repeat steps 5, 6, and 8. b.If there is no further data, set Control [HOLD] bit = 0. 9.Wait for the completion of transfer. Check that the ISR [COMP] register bit is set = 1.