Sync and Async Abort

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
Release Date
2.4 English

To understand the sync and async abort, consider the example application running in the APU domain that generates two types of interrupts: sync and error aborts. The actual error type depends on the corresponding transaction type (read or write) and each must have their own handler. The requirements for two types of errors comes from the Arm architecture itself, not the AMD-specific implementation. Handling these errors is up to the developer and the requirements of the system being developed. See Isolation Methods in Zynq UltraScale+ MPSoCs (XAPP1320) [Ref 38] for more information.

Transaction Poisoning

Transaction poisoning can be accomplished by the following.

Force the outgoing AxADDR [48:32] to zeros.

Replace the incoming AxADDR[31:12] with LPD_XPPU.POISON[BASE].

Keep the incoming AxADDR[11:0] intact.

On the system address map, a 4 KB size sink module at address {17'b0, LPD_XPPU.POISON[BASE] 12'b0} is present, which takes a poisoned transaction, returns an error response, and optionally records the lower 12 bits of the transaction address. This can cause either a data abort or an interrupt to the processor.

Note:   The poisoned reads return value of all zeros and poisoned writes are ignored. To make the system aware of transaction poisoning, generation of a slave error response can be enabled using the XPPU_SINK.ERR_CTRL[PSLVERR] bit.

Figure 16-7:      XPPU Address Poison Block Diagram

X-Ref Target - Figure 16-7