Initialization Vector Register

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
Release Date
2.4 English

The four initialization vector (IV) registers combined create a larger 128 bit value. This 128-bit values contains two separate fields. The first field resides in the first three AES IV registers (aes_iv_0, aes_iv_1, and aes_iv_2) and contains the 96-bit AES-GCM initialization vector (IV). The 96-bit AES-GCM IV is specified by the AES-GCM standard and initializes the counts used in this AES mode. The fourth register (aes_iv_3) contains the decrypt length count (DLC). The DLC specifies the data size of the next block. The DLC is used when the key rolling feature is enabled in the boot image. Table: Initialization Vector Format shows the IV vector format.

Table 12-12:      Initialization Vector Format

127                                                                 32                 0


(Decrypt length count)

96-bit random value

Next block data size (key rolling)