Zynq UltraScale+ Device Technical Reference Manual (UG1085)

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The Zynq UltraScale+™ RFSoC family integrates key subsystems for multiband, multi-mode cellular radios and cable infrastructure (DOCSIS) into an SoC platform that contains a feature-rich 64-bit quad-core Arm® Cortex™-A53 and dual-core Arm Cortex-R5F based processing system.

A brief introduction is included in this section. For more information, see the Zynq UltraScale+ RFSoC RF Data Converter LogiCORE IP Product Guide (PG252) [Ref 26].

Combining the processing system with UltraScale™ architecture programmable logic and RF-ADCs, RF-DACs, and soft-decision FECs, the Zynq UltraScale+ RFSoC family is capable of implementing a complete software-defined radio including direct RF sampling data converters, enabling CPRI™ and gigabit Ethernet-to-RF on a single, highly programmable SoC.

Zynq UltraScale+ RFSoCs integrate up to 16 channels of RF-ADCs and RF-DACs. The RF-ADCs can sample input frequencies up to 4 GHz at 4.096 GSPS with excellent noise spectral density. The RF-DACs generate output carrier frequencies up to 4 GHz using the 2nd Nyquist zone with excellent noise spectral density at an update rate of 6.554 GSPS. The RF data converters also include power efficient digital down converters (DDCs) and digital up converters (DUCs) that include programmable interpolation and decimation, NCO, and complex mixer. The DDCs and DUCs can also support dual-band operation.

The soft-decision FEC (SD-FEC) is a highly flexible forward error correction engine capable of operating in Turbo decoding mode for wireless applications such as LTE and LDPC encode/decode mode used in 5G wireless, backhaul, and DOCSIS 3.1 cable modems.

This Figure shows the key components of the Zynq UltraScale+ RFSoC devices.

Figure 36-2:      Zynq UltraScale+ RFSoC

X-Ref Target - Figure 36-2