I2C Interface Programming Example

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID

UG1085

Release Date

2023-12-21

Revision

2.4 English

The MIO can be configured to route the I2C interface signals to MIO pins 2 and 3. To route the I2C SCL signal to MIO pin 2, write 'h40 to the IOU_SLCR.MIO_PIN_2 register. To route the I2C SDA signal to MIO pin 3, write 'h40 to the IOU_SLCR.MIO_PIN_3 register.

The MIO pins and their signal names for each interface are listed in Table: MIO Interfaces.Table 28-4: MIO Interfaces
	Interface Type
	gem0	gem1	gem2	gem3	gem_tsu	qspi⁽²⁾	nand	pcie⁽³⁾	usb0	usb1	pmu	sd0⁽¹⁾	sd1⁽¹⁾	test_scan	csu	dpaux	gpio0	gpio1	gpio2	can0	can1	i2c0	i2c1	mdio0	pjtag	lpd_ swdt	fpd_ swdt	mdio1	spi0	spi1	mdio2	ttc0	ttc1	ttc2	ttc3	mdio3	ua0	ua1	trace
Size	12	12	12	12	1	13	17	1	12	12	12	13	13	38	1	4	26	26	26	2	2	2	2	2	4	2	2	2	6	6	2	2	2	2	2	2	2	2	18
Pin
0						sclk_out 4								io[0] 0			io[0] 0				phy_tx 1		scl 0		tck 3				sclk 5						clk 0			txd 1	clk 0
1						io[1] 1								io[1] 1			io[1] 1				phy_rx 0		sda 1		tdi 0				n_ss_out[2] 4						wave_out 1			rxd 0	clk 1
2						io[2] 2								io[2] 2			io[2] 2			phy_rx 0		scl 0			tdo 1				n_ss_out[1] 3					clk 0			rxd 0		dq_0 2
3						io[3] 3								io[3] 3			io[3] 3			phy_tx 1		sda 1			tms 2				n_ss_out[0] 2					wave_out 1			txd 1		dq_1 3
4						si_mio[0] 0								io[4] 4			io[4] 4				phy_tx 1		scl 0				clk_in 0		miso 1				clk 0					txd 1	dq_2 4
5						n_ss_out 5								io[5] 5			io[5] 5				phy_rx 0		sda 1				rst_out 1		mosi 0				wave_out 1					rxd 0	dq_3 5
6						clk_for_lpbk 12								io[6] 6			io[6] 6			phy_rx 0		scl 0				clk_in 0				sclk 5		clk 0					rxd 0		dq_4 6
7						n_ss_out_ upper 6								io[7] 7			io[7] 7			phy_tx 1		sda 1				rst_out 1				n_ss_out[2] 4		wave_out 1					txd 1		dq_5 7
8						upper _io[0] 8								io[8] 8			io[8] 8				phy_tx 1		scl 0				clk_in 0			n_ss_out[1] 3					clk 0			txd 1	dq_6 8
9						upper _io[1] 9	ce[1] 2							io[9] 9			io[9] 9				phy_rx 0		sda 1				rst_out 1			n_ss_out[0] 2					wave_out 1			rxd 0	dq_7 9
10						upper _io[2] 10	rb_n[0] 13							io[10] 10			io[10] 10			phy_rx 0		scl 0				clk_in 0				miso 1				clk 0			rxd 0		dq_8 10
11						upper _io[3] 11	rb_n[1] 14							io[11] 11			io[11] 11			phy_tx 1		sda 1				rst_out 1				mosi 0				wave_out 1			txd 1		dq_9 11
12						sclk_ out_ upper 7	dqs 4							io[12] 12		.	io[12] 12				phy_tx 1		scl 0		tck 3				sclk 5				clk 0					txd 1	dq_10 12
13							ce[0] 1					data_io[0] 4		io[13] 13			io[13] 13				phy_rx 0		sda 1		tdi 0				n_ss_out[2] 4				wave_out 1					rxd 0	dq_11 13
14							cle 3					data_io[1] 5		io[14] 14			io[14] 14			phy_rx 0		scl 0			tdo 1				n_ss_out[1] 3			clk 0					rxd 0		dq_12 14
15							ale 0					data_io[2] 6		io[15] 15			io[15] 15			phy_tx 1		sda 1			tms 2				n_ss_out[0] 2			wave_out 1					txd 1		dq_13 15
16							dq[0] 5					data_io[3] 7		io[16] 16			io[16] 16				phy_tx 1		scl 0				clk_in 0		miso 1						clk 0			txd 1	dq_14 16
17							dq[1] 6					data_io[4] 8		io[17] 17			io[17] 17				phy_rx 0		sda 1				rst_out 1		mosi 0						wave_out 1			rxd 0	dq_15 17
18							dq[2] 7					data_io[5] 9		io[18] 18	ext_ tamper 0		io[18] 18			phy_rx 0		scl 0				clk_in 0				miso 1				clk 0			rxd 0
19							dq[3] 8					data_io[6] 10		io[19] 19	ext_ tamper 0		io[19] 19			phy_tx 1		sda 1				rst_out 1				n_ss_out[2] 4				wave_out 1			txd 1
20							dq[4] 9					data_io[7] 11		io[20] 20	ext_ tamper 0		io[20] 20				phy_tx 1		scl 0				clk_in 0			n_ss_out[1] 3			clk 0					txd 1
21							dq[5] 10					cmd_io 3		io[21] 21	ext_ tamper 0		io[21] 21				phy_rx 0		sda 1				rst_out 1			n_ss_out[0] 2			wave_out 1					rxd 0
22							we_b 16					clk_out 2		io[22] 22	ext_ tamper 0		io[22] 22			phy_rx 0		scl 0				clk_in 0				sclk 5		clk 0					rxd 0
23							dq[6] 11					bus_pow 13		io[23] 23	ext_ tamper 0		io[23] 23			phy_tx 1		sda 1				rst_out 1				mosi 0		wave_out 1					txd 1
24							dq[7] 12					cd_n 1		io[24] 24	ext_ tamper 0		io[24] 24				phy_tx 1		scl 0				clk_in 0								clk 0			txd 1
25							re_n 15					wp 0		io[25] 25	ext_ tamper 0		io[25] 25				phy_rx 0		sda 1				rst_out 1								wave_out 1			rxd 0
26	rgmii_ tx_clk 0				gem_ tsu_clk 0		ce[1] 2				gpi[0] 0			io[26] 26	ext_ tamper 0			io[0] 0		phy_rx 0		scl 0			tck 3				sclk 5					clk 0			rxd 0		dq_4 6
27	rgmii_ txd[0] 1						rb_n[0] 13				gpi[1] 1			io[27] 27		data_ out 0		io[1] 1		phy_tx 1		sda 1			tdi 0				n_ss_out[2] 4					wave_out 1			txd 1		dq_5 7
28	rgmii_txd[1] 2						rb_n[1] 14				gpi[2] 2			io[28] 28		hot_plug_detect 1		io[2] 2			phy_tx 1		scl 0		tdo 1				n_ss_out[1] 3				clk 0					txd 1	dq_6 8
29	rgmii_txd[2] 3							reset_n 0			gpi[3] 3			io[29] 29		data_oe 2		io[3] 3			phy_rx 0		sda 1		tms 2				n_ss_out[0] 2				wave_out 1					rxd 0	dq_7 9
30	rgmii_txd[3] 4							reset_n 0			gpi[4] 4			io[30] 30		data_in 3		io[4] 4		phy_rx 0		scl 0				clk_in 0			miso 1			clk 0					rxd 0		dq_8 10
31	rgmii_tx_ctl 5							reset_n 0			gpi[5] 5			io[31] 31	ext_tamper 0			io[5] 5		phy_tx 1		sda 1				rst_out 1			mosi 0			wave_out 1					txd 1		dq_9 11
32	rgmii_rx_clk 6						dqs 4				gpo[0] 6			io[32] 32	ext_tamper 0			io[6] 6			phy_tx 1		scl 0				clk_in 0			sclk 5					clk 0			txd 1	dq_10 12
33	rgmii_rxd[0] 7							reset_n 0			gpo[1] 7			io[33] 33	ext_tamper 0			io[7] 7			phy_rx 0		sda 1				rst_out 1			n_ss_out[2] 4					wave_out 1			rxd 0	dq_11 13
34	rgmii_rxd[1] 8							reset_n 0			gpo[2] 8			io[34] 34		data_out 0		io[8] 8		phy_rx 0		scl 0				clk_in 0				n_ss_out[1] 3				clk 0			rxd 0		dq_12 14
35	rgmii_rxd[2] 9							reset_n 0			gpo[3] 9			io[35] 35		hot_plug_detect 1		io[9] 9		phy_tx 1		sda 1				rst_out 1				n_ss_out[0] 2				wave_out 1			txd 1		dq_13 15
36	rgmii_rxd[3] 10							reset_n 0			gpo[4] 10			io[36] 36		data_oe 2		io[10] 10			phy_tx 1		scl 0				clk_in 0			miso 1			clk 0					txd 1	dq_14 16
37	rgmii_rx_ctl 11							reset_n 0			gpo[5] 11			io[37] 37		data_in 3		io[11] 11			phy_rx 0		sda 1				rst_out 1			mosi 0			wave_out 1					rxd 0	dq_15 17
38		rgmii_tx_clk 0										clk_out 2						io[12] 12		phy_rx 0		scl 0			tck 3				sclk 5			clk 0					rxd 0		clk 0
39		rgmii_txd[0] 1										cd_n 1	data_io[4] 8					io[13] 13		phy_tx 1		sda 1			tdi 0				n_ss_out[2] 4			wave_out 1					txd 1		clk 1
40		rgmii_txd[1] 2										cmd_io 3	data_io[5] 9					io[14] 14			phy_tx 1		scl 0		tdo 1				n_ss_out[1] 3						clk 0			txd 1	dq_0 2
41		rgmii_txd[2] 3										data_io[0] 4	data_io[6] 10					io[15] 15			phy_rx 0		sda 1		tms 2				n_ss_out[0] 2						wave_out 1			rxd 0	dq_1 3
42		rgmii_txd[3] 4										data_io[1] 5	data_io[7] 11					io[16] 16		phy_rx 0		scl 0				clk_in 0			miso 1					clk 0			rxd 0		dq_2 4
43		rgmii_tx_ctl 5										data_io[2] 6	bus_pow 13					io[17] 17		phy_tx 1		sda 1				rst_out 1			mosi 0					wave_out 1			txd 1		dq_3 5
44		rgmii_rx_clk 6										data_io[3] 7	wp 0					io[18] 18			phy_tx 1		scl 0				clk_in 0			sclk 5			clk 0					txd 1
45		rgmii_rxd[0] 7										data_io[4] 8	cd_n 1					io[19] 19			phy_rx 0		sda 1				rst_out 1			n_ss_out[2] 4			wave_out 1					rxd 0
46		rgmii_rxd[1] 8										data_io[5] 9	data_io[0] 4					io[20] 20		phy_rx 0		scl 0				clk_in 0				n_ss_out[1] 3		clk 0					rxd 0
47		rgmii_rxd[2] 9										data_io[6] 10	data_io[1] 5					io[21] 21		phy_tx 1		sda 1				rst_out 1				n_ss_out[0] 2		wave_out 1					txd 1
48		rgmii_rxd[3] 10										data_io[7] 11	data_io[2] 6					io[22] 22			phy_tx 1		scl 0				clk_in 0			miso 1					clk 0			txd 1
49		rgmii_rx_ctl 11										bus_pow 13	data_io[3] 7					io[23] 23			phy_rx 0		sda 1				rst_out 1			mosi 0					wave_out 1			rxd 0
50					gem_tsu_clk 0							wp 0	cmd_io 3					io[24] 24		phy_rx 0		scl 0				clk_in 0		gem1_mdc 0						clk 0			rxd 0
51					gem_tsu_clk 0								clk_out 2					io[25] 25		phy_tx 1		sda 1				rst_out 1		gem1_mdio 1						wave_out 1			txd 1
52			rgmii_tx_clk 0						ulpi_clk_in 0										io[0] 0		phy_tx 1		scl 0		tck 3				sclk 5				clk 0					txd 1	clk 0
53			rgmii_txd[0] 1						ulpi_dir 1										io[1] 1		phy_rx 0		sda 1		tdi 0				n_ss_out[2] 4				wave_out 1					rxd 0	clk 1
54			rgmii_txd[1] 2						ulpi_rx_data[2] 6										io[2] 2	phy_rx 0		scl 0			tdo 1				n_ss_out[1] 3			clk 0					rxd 0		dq_0 2
55			rgmii_txd[2] 3						ulpi_nxt 3										io[3] 3	phy_tx 1		sda 1			tms 2				n_ss_out[0] 2			wave_out 1					txd 1		dq_1 3
56			rgmii_txd[3] 4						ulpi_rx_data[0] 4										io[4] 4		phy_tx 1		scl 0				clk_in 0		miso 1						clk 0			txd 1	dq_2 4
57			rgmii_tx_ctl 5						ulpi_rx_data[1] 5										io[5] 5		phy_rx 0		sda 1				rst_out 1		mosi 0						wave_out 1			rxd 0	dq_3 5
58			rgmii_rx_clk 6						ulpi_stp 2										io[6] 6	phy_rx 0		scl 0			tck 3					sclk 5				clk 0			rxd 0		dq_4 6
59			rgmii_rxd[0] 7						ulpi_rx_data[3] 7										io[7] 7	phy_tx 1		sda 1			tdi 0					n_ss_out[2] 4				wave_out 1			txd 1		dq_5 7
60			rgmii_rxd[1] 8						ulpi_rx_data[4] 8										io[8] 8		phy_tx 1		scl 0		tdo 1					n_ss_out[1] 3			clk 0					txd 1	dq_6 8
61			rgmii_rxd[2] 9						ulpi_rx_data[5] 9										io[9] 9		phy_rx 0		sda 1		tms 2					n_ss_out[0] 2			wave_out 1					rxd 0	dq_7 9
62			rgmii_rxd[3] 10						ulpi_rx_data[6] 10										io[10] 10	phy_rx 0		scl 0				clk_in 0				miso 1		clk 0					rxd 0		dq_8 10
63			rgmii_rx_ctl 11						ulpi_rx_data[7] 11										io[11] 11	phy_tx 1		sda 1				rst_out 1				mosi 0		wave_out 1					txd 1		dq_9 11
64				rgmii_tx_clk 0						ulpi_clk_in 0		clk_out 2							io[12] 12		phy_tx 1		scl 0				clk_in 0		sclk 5						clk 0			txd 1	dq_10 12
65				rgmii_txd[0] 1						ulpi_dir 1		cd_n 1							io[13] 13		phy_rx 0		sda 1				rst_out 1		n_ss_out[2] 4						wave_out 1			rxd 0	dq_11 13
66				rgmii_txd[1] 2						ulpi_rx_data[2] 6		cmd_io 3							io[14] 14	phy_rx 0		scl 0				clk_in 0			n_ss_out[1] 3					clk 0			rxd 0		dq_12 14
67				rgmii_txd[2] 3						ulpi_nxt 3		data_io[0] 4							io[15] 15	phy_tx 1		sda 1				rst_out 1			n_ss_out[0] 2					wave_out 1			txd 1		dq_13 15
68				rgmii_txd[3] 4						ulpi_rx_data[0] 4		data_io.[1] 5							io[16] 16		phy_tx 1		scl 0				clk_in 0		miso 1				clk 0					txd 1	dq_14 16
69				rgmii_tx_ctl 5						ulpi_rx_data[1] 5		data_io [2] 6	wp 0						io[17] 17		phy_rx 0		sda 1				rst_out 1		mosi 0				wave_out 1					rxd 0	dq_15 17
70				rgmii_rx_clk 6						ulpi_stp 2		data_io [3] 7	bus_pow 13						io[18] 18	phy_rx 0		scl 0				clk_in 0				sclk 5		clk 0					rxd 0
71				rgmii_rxd[0] 7						ulpi_rx_data[3] 7		data_io [4] 8	data_io [0] 4						io[19] 19	phy_tx 1		sda 1				rst_out 1				n_ss_out[2] 4		wave_out 1					txd 1
72				rgmii_rxd[1] 8						ulpi_rx_data[4] 8		data_io [5] 9	data_io [1] 5						io[20] 20		phy_tx 1		scl 0				clk_in 0			n_ss_out[1] 3								txd 1
73				rgmii_rxd[2] 9						ulpi_rx_data[5] 9		data_io[6] 10	data_io[2] 6						io[21] 21		phy_rx 0		sda 1				rst_out 1			n_ss_out[0] 2								rxd 0
74				rgmii_rxd[3] 10						ulpi_rx_data[6] 10		data_io[7] 11	data_io[3] 7						io[22] 22	phy_rx 0		scl 0				clk_in 0				miso 1							rxd 0
75				rgmii_rx_ctl 11						ulpi_rx_data[7] 11		bus_pow 13	cmd_io 3						io[23] 23	phy_tx 1		sda 1				rst_out 1				mosi 0							txd 1
76												wp 0	clk_out 2						io[24] 24		phy_tx 1		scl 0	gem0_mdc 0				gem1_mdc 0			gem2_mdc 0					gem3_mdc 0
77													cd_n 1						io[25] 25		phy_rx 0		sda 1	gem0_mdio 1				gem1_mdio 1			gem2_mdio 1					gem3_mdio 1
Notes: 1.SD0/1 peripheral pins can also be configured as eMMC 0/1, respectively. The difference between SD and eMMC configuration is as follows. °The Card Detect and Write Protect signals are only available in SD mode. °The BUS_POW pin in SD mode is treated as a reset pin in eMMC mode. °In SD mode, data transfers in 1-bit and 4-bit modes. In eMMC mode, data transfers in 1-bit, 4-bit, and 8-bit modes. °If the SD interface is configured for SD 3.0, the signals SEL, DIR_CMD, DIR_0, and DIR_1_3 are mapped to data_io[4], data_io[5], data_io[6], and data_io[7], respectively. 2.In Quad-SPI loopback mode, leave the clk_for_lpbk signal floating. In Quad-SPI non-loopback mode, the clk_for_lpbk signal is not used by the Quad-SPI and can be used as a peripheral I/O (such as GPIO, CAN, or I2C). 3.The PCIe Root Port mode reset signals are routed to specific MIO pins as listed in Table: PCIe Reset Signals on MIO.