Controller Initialization

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

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2.4 English

The controller initialization sequence has the following phases.

PHY initialization

DRAM initialization

Data training

This Figure and This Figure show high-level illustrations of the initialization sequence of the PHY.

Figure 17-9:      PHY Initialization Sequence

X-Ref Target - Figure 17-9

Figure 17-10:      PHY Initialization Sequence (Continued)

X-Ref Target - Figure 17-10


Impedance calibration failures can be caused by an open or short on the PS_DDR_ZQ pin.  Double check to ensure PS_DDR_ZQ is connected to GND with a 240Ω resistor. There should be separate 240Ω resistors at the FPGA and the DRAM.