|
Task
|
SERDES Register Set
|
Bit Field
|
Register Offset
|
Bits
|
Value
|
|
SSC turn off for L0
|
L0_PLL_FBDIV_FRAC_3_MSB
|
[tm_force_en_frac]
|
0x2360
|
6
|
1b'1
|
|
SSC turn off for L0
|
L0_PLL_SS_STEP_SIZE_3_MSB
|
[tm_force_en_ss]
|
0x237C
|
7
|
1b'1
|
|
SSC turn off for L1
|
L1_PLL_FBDIV_FRAC_3_MSB
|
[tm_force_en_frac]
|
0x6360
|
6
|
1b'1
|
|
SSC turn off for L1
|
L1_PLL_SS_STEP_SIZE_3_MSB
|
[tm_force_en_ss]
|
0x637C
|
7
|
1b'1
|
|
SSC turn off for L2
|
L2_PLL_FBDIV_FRAC_3_MSB
|
[tm_force_en_frac]
|
0xA360
|
6
|
1b'1
|
|
SSC turn off for L2
|
L2_PLL_SS_STEP_SIZE_3_MSB
|
[tm_force_en_ss]
|
0xA37C
|
7
|
1b'1
|
|
SSC turn off for L3
|
L3_PLL_FBDIV_FRAC_3_MSB
|
[tm_force_en_frac]
|
0xE360
|
6
|
1b'1
|
|
SSC turn off for L3
|
L3_PLL_SS_STEP_SIZE_3_MSB
|
[tm_force_en_ss]
|
0xE37C
|
7
|
1b'1
|
|
For PORT0
|
|
Select lane0 for SATA0
|
ICM_CFG0
|
[L0_icm_cfg]
|
0x0010
|
2:0
|
3b'010
|
|
PM clock frequency selection for 150 MHz
|
PLL_REF_SEL0
|
[pllrefsel0]
|
0x0000
|
4:0
|
0x11
|
|
PM clock frequency selection for 300 MHz
|
0x0000
|
4:0
|
0x01
|