Example: Transmitting a Frame

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

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1.Allocate buffers in system memory to contain the Ethernet frame. Gigabit Ethernet supports scatter-gather functionality; an Ethernet frame can be split into multiple buffers with each buffer processed by a buffer descriptor.

2.Write the Ethernet frame data in the allocated buffers. These Ethernet frames should have their header fields such as destination MAC address, source MAC address, and type/length field set appropriately.

°The FCS field is added by the MAC in most cases. However, if there is a need to append a custom FCS, bit [16] in word [1] of the corresponding buffer descriptor must be set.

°The buffer that contains the Ethernet frame data should be flushed from cache if cached memory is being used.

3.Allocate buffer descriptor(s) for the Ethernet frame buffers. This involves setting bits [0-31] in the buffer descriptor word [0] with the address of the buffer and setting bits [0-13] in word [1] with the length of the buffer to be transmitted.

°For single buffer Ethernet frames, bit [15] (last buffer bit) of the word [1] must also be set.

°For Ethernet frames scattered across multiple buffers the buffer descriptors must be allocated serially and the buffer descriptor containing the last buffer should have the bit [15] of word [1] set.

Example: For an Ethernet frame of 1,000 bytes split across two buffers with the first buffer containing the Ethernet header (14 bytes) and the next buffer containing the remaining 986 bytes, the buffer descriptor with index N should be allocated for the first buffer and the buffer descriptor with index N+1 should be allocated for the second buffer. Bit [15] of word [1] of the N+1 buffer descriptor must also be set to mark it as the last buffer in the scattered list of Ethernet frames.

4.Clear the used bit, (bit [31]), in the word [1] of the allocated buffer descriptors.


RECOMMENDED:   Clear the used bit (bit[31]) of the first buffer descriptor after clearing all the descriptors in the chain.

5.Enable transmission. Write a 1 to gem.network_control[tx_start_pclk].

6.Wait until the transmission is complete. An interrupt is generated by the controller upon successful completion of the transmission. Successful transmission can be determined by reading the gem.int_status [transmit_complete] bit as a 1. By reading this register, the [transmit_complete] bit is cleared by the hardware. Also read and clear the gem.transmit_status register by writing a 1 to gem.transmit_status[transmit_complete] bit. Clear all bits in the buffer descriptor (BD) except the used and wrap bits.