The accelerator coherency port (ACP) is a 128-bit AXI slave interface on the snoop control unit (SCU) that provides an asynchronous cache-coherent access point directly from the PL to the APU. Several PL masters can use this interface to access the caches and the memory subsystem in the same way the APU processors use to simplify software, increase overall system performance, or improve power consumption.
From a system perspective, the ACP interface has connectivity similar to the APU CPUs. Due to this close connectivity, the ACP directly competes with them for resource access outside of the APU MPCore.
TIP: All ACP transactions are considered coherent to the APU L1 data cache and L2 unified cache. There is no option to mark a transaction as non-coherent through the side band signals (AxUSER and AxCACHE).
Any read transactions through the ACP to a coherent region of memory interact with the SCU to check whether the required information is stored within the processor L1 data caches. If it is, the data is returned directly to the requesting component. If it misses in the L1 cache, then there is also the opportunity to hit in L2 cache before finally being forwarded to the DDR memory. For write transactions to any coherent memory region, the SCU enforces coherency before the write is forwarded to the DDR memory system. The transaction can also optionally allocate into the L2 cache, removing the power and performance impact of writing through to the DDR memory.
The ACP accesses do not go through either the APU's MMU or the System's SMMU, hence, their request-address is a 40-bit physical address.
IMPORTANT: Since the PL-ACE does not have an AXI FIFO interface to regulate sending write data with or before the write command, care must be taken when choosing a master. Failure to choose a master that presents data before or along with the write command can lead to starvation and other system level issues.