Each system PLL unit has a clock divider in its own power domain and one in the other power domain. Both sets of dividers are represented as boxes in This Figure and the controls for the power-domain crossed clocks are shown in This Figure.
Each system PLL unit has a clock divider in its own power domain and one in the other power domain. Both sets of dividers are represented as boxes in This Figure and the controls for the power-domain crossed clocks are shown in This Figure.
