The dedicated power pins for the PS and internal logic of the PL are listed in Table: Power Pins. See Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925) [Ref 2] for specifications.
Table 2-1: Power Pins
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Pin Name
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Description
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VCC_PSINTLP
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PS low-power domain (LPD) supply voltage.
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VCC_PSINTFP
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PS full-power domain (FPD) supply voltage.
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VCC_PSAUX
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PS auxiliary voltage.
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VCC_PSBATT
|
PS battery operated voltage.
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VCC_PSPLL
|
LPD PLLs: RPLL (RPU), IOPLL (I/O).
FPD PLLs: APLL (APU), VPLL (video), DPLL (DDR controller).
|
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VCC_PSDDR_PLL
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DDR PLLs supply voltage for DDRIOB. When PS DDR is not used, tie to ground.
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VCC_PSINTFP_DDR
|
DDR memory controller supply voltage. Tie to VCC_PSINTFP.
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VCCO_PSDDR
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PS DDR I/O supply voltage. When PS DDR is not used, tie to ground.
|
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VCCO_PSIO[0:3]
|
Power supply voltage for the PS I/O banks.
•VCCO_PSIO[0] is bank 500. MIO pins 0 to 25.
•VCCO_PSIO[1] is bank 501. MIO pins 26 to 51.
•VCCO_PSIO[2] is bank 502. MIO pins 52 to 77.
•VCCO_PSIO[3] is bank 503. Mode, config, PSJTAG, error, SRST, POR, PS_REF_CLK.
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VCCINT
|
PL power domain (PLPD) supply voltage.
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VCCINT_VCU
|
Video codec unit supply voltage.
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VCCAUX
|
PL auxiliary voltage.
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VCCBRAM
|
PL block RAM supply voltage.
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PS_MGTRAVCC
|
PS-GTR VMGTAVCC supply voltage.
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PS_MGTRAVTT
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PS GTR VMGTAVTT termination voltage.
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VCC_PSADC
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PS System Monitor analog voltage.
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VCCADC
|
PL System Monitor analog voltage.
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