The following sequence is used to enable the lock-step mode of the Cortex-R5F processors.
;SVC out of reset
MOV r0,#0
MOV r1,#0
MOV r2,#0
MOV r3,#0
MOV r4,#0
MOV r5,#0
MOV r6,#0
MOV r7,#0
MOV r8,#0
MOV r9,#0
MOV r10,#0
MOV r11,#0
MOV r12,#0
MOV r13,#0x10000
;SP - Choose a suitable stack pointer value based on your system
MOV r14, #0;LR
;User (Sys)
MSR CPSR_cxsf,#0x1F
MOV r13,#0x70000
;SP - Choose a suitable stack pointer value based on your system
MOV r14,#0;LR
;FIQ
MSR CPSR_cxsf,#0x11
MOV r8,#0
MOV r9,#0
MOV r10,#0
MOV r11,#0
MOV r12,#0
MOV r13,#0x60000
;SP - Choose a suitable stack pointer value based on your system
MOV r14,#0;LR
;IRQ
MSR CPSR_cxsf,#0x12
MOV r13,#0x50000
;SP - Choose a suitable stack pointer value based on your system
MOV r14,#0;LR
;Undef
MSR CPSR_cxsf,#0x1B
MOV r13,#0x40000
;SP - Choose a suitable stack pointer value based on your system
MOV r14,#0;LR
;Abort
MSR CPSR_cxsf,#0x17
MOV r13, #0x30000
;SP - Choose a suitable stack pointer value based on your system
MOV r14, #0;LR
;Return to SVC
MSR CPSR_cxsf,#0x13
FUNC(asm_init_vfp_regs)
mov>----r1,#0
vmov d0,r1,r1
vmov d1,r1,r1
vmov d2,r1,r1
vmov d3,r1,r1
vmov d4,r1,r1
vmov d5,r1,r1
vmov d6,r1,r1
vmov d7,r1,r1
vmov d8,r1,r1
vmov d9,r1,r1
vmov d10,r1,r1
vmov d11,r1,r1
vmov d12,r1,r1
vmov d13,r1,r1
vmov d14,r1,r1
vmov d15,r1,r1
cmp r0,#1
beq asm_init_vfp_regs32
bx lr
asm_init_vfp_regs32:
vmov d16,r1,r1
vmov d17,r1,r1
vmov d18,r1,r1
vmov d19,r1,r1
vmov d20,r1,r1
vmov d21,r1,r1
vmov d22,r1,r1
vmov d23,r1,r1
vmov d24,r1,r1
vmov d25,r1,r1
vmov d26,r1,r1
vmov d27,r1,r1
vmov d28,r1,r1
vmov d29,r1,r1
vmov d30,r1,r1
vmov d31,r1,r1
bx lr
The ECC for the cache RAMs is initialized as part of the initial invalidation after reset. The cache ECC checking must be enabled during the invalidation using the following sequence.
DSB
MRC p15, 0, r1, c1, c0, 1 ;Read ACTLR
ORR r1, r1, #(0x1 << 5) ;Set Bits [5:3] = 0b101
BIC r1, r1, #(0x1 << 4) ;to enable ECC no forced
ORR r1, r1, #(0x1 << 3) ;write-through
MCR p15, 0, r1, c1, c0, 1 ;Write ACTLR ISB
MCR p15, 0, r0, c7, c5, 0 ;Invalidate All instruction caches
MCR p15, 0, r0, c15, c5, 0 ;Invalidate All Data caches DSB ISB
If you have ECC on the TCMs, then the initial accesses to the TCM locations also needs to ensure that the ECC locations are updated correctly.