The reference clock network architecture has four lanes (PS_MGTREFCLK0, PS_MGTREFCLK1, PS_MGTREFCLK2, and PS_MGTREFCLK3 also referred as Ref Clk [0, 1, 2, 3 in GUI) and supports multiple protocols at each lane independently. The reference clock frequencies required to support various protocols are listed in Table: Reference Clock per Protocol. Each lane can be programmed through the PCW under Clock Configurations to have its own reference clock, or share a reference clock from another lane. For more information regarding the reference clock frequencies, refer to the Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925) [Ref 2].
Note: GTR reference clock PS_MGTREFCLKP/N should be stable before releasing the PS_POR_B, just like PS_REF_CLK.