Reference Clock Network

Zynq UltraScale+ Device Technical Reference Manual (UG1085)
Document ID
UG1085
Release Date
2023-12-21
Revision
2.4 English

The reference clock network architecture has four lanes (PS_MGTREFCLK0, PS_MGTREFCLK1, PS_MGTREFCLK2, and PS_MGTREFCLK3 also referred as Ref Clk [0, 1, 2, 3 in GUI) and supports multiple protocols at each lane independently. The reference clock frequencies required to support various protocols are listed in Table: Reference Clock per Protocol. Each lane can be programmed through the PCW under Clock Configurations to have its own reference clock, or share a reference clock from another lane. For more information regarding the reference clock frequencies, refer to the Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925) [Ref 2].

Table 29-2:      Reference Clock per Protocol

Protocol

Reference Clock Frequency (MHz)

PCIe v2.0 (multi-lane)

Only the common clock architecture is supported.

100.0 MHz

SATA (multi-core)

125.0 MHz, 150.0 MHz

USB 3.0

26.0 MHz, 52.0 MHz, 100.0 MHz

DisplayPort (harmonic of 27.0 MHz)

27.0 MHz, 108.0 MHz, 135.0 MHz

GEM SGMII, 1000BASE-SX, or 1000BASE-LX

125.0 MHz

Note:   GTR reference clock PS_MGTREFCLKP/N should be stable before releasing the PS_POR_B, just like PS_REF_CLK.