•Low-level (generic) access
•3, 4, 6,…n-byte addresses
•SPI NAND flash devices
•Command queuing (generic FIFO depth is 32)
•4- or 8-bit interface
•Two chip-select lines
•4-bit bidirectional I/O signals
•x1, x2, and x4 read/write
•44-bit address space on AXI in DMA mode
•Byte stripe when two data buses are connected
•Single system interrupt for controller/DMA interrupt status (IRQ 47)
•Single transfer rate (STR) mode
•64-word RXFIFO, 64-word TXFIFO