The Zynq UltraScale+ MPSoC device is divided between the PS and PL. There are several units in the PL that have special wiring connections to the PS and the PL I/O pins. The units are powered by PL voltage pins. The PL fabric can be configured using the UltraScale+ LogiCORE™ soft IP.
Table 1-5: Document Matrix
|
Document
|
System Architect
|
PCB Design
|
System Software
|
Host Software
|
Description/
Audience Relative
to the TRM
|
|
PMU FW, FSBL, Drivers
|
Linux, Other
|
|
Technical Reference Manual
|
UG1085
|
Yes
|
Pin functions
|
PS functionality
|
Architecture
|
Architecture, functionality,
and control.
|
|
Data Sheet: Overview
|
DS891
|
Start here
|
Overview
|
Overview
|
~
|
Introductions of all the
system elements in the
PS and PL.
|
|
MPSoC Data Sheet:
DC and AC
|
DS925
|
Frequencies
|
AC/DC spec.
|
~
|
~
|
PCB designer.
|
|
RFSoC Data Sheet:
DC and AC
|
DS926
|
Frequencies
|
AC/DC spec.
|
~
|
~
|
PCB designer.
|
|
PCB Design User Guide
|
UG583
|
~
|
Yes
|
~
|
~
|
PCB designer.
|
|
System Monitor User Guide
|
UG580
|
~
|
Analog inputs
|
Yes
|
~
|
Explains the core functionality of the SYSMON units.
|
|
Online Register Reference
|
UG1087
|
~
|
~
|
Yes
|
~
|
Register sets (modules) descriptions.
|
|
Software Developer Guide
|
UG1137
|
Functionality
|
~
|
Yes
|
Yes
|
System software features.
|
|
PS LogiCORE IP Product Guide
|
PG201
|
PS-PL interface
|
~
|
~
|
~
|
Integration using Vivado design tools.
|
|
Packaging and Pinouts Spec.
|
UG1075
|
~
|
Yes
|
~
|
~
|
Defines DDR to DRAM I/O connections.
|
|
Product Data Sheet: Overview
|
DS890
|
Perspective
|
~
|
Perspective
|
~
|
All UltraScale and UltraScale+ devices.
|
|
PL-based MPSoC units
|
Several
|
Functionality per device
|
GTR
|
Yes
|
~
|
Examples:
VCU, PCIe, 100 Gbit.
|
|
PL-based FPGA units
|
Many
|
PL Instantiations
|
SelectIO
|
~
|
~
|
Examples:
DSP, LUT, block RAM.
|
|
OS and Libraries Document Collection
|
UG643
|
Yes
|
~
|
Yes
|
Yes
|
System and application programmer.
|
This technical reference manual (TRM) describes the architecture and functionality of the PS and parts of the PL. The TRM is a foundation for the Zynq UltraScale+ MPSoC Software Developer’s Guide (UG1137) [Ref 3] and other application guides. The PS control registers are defined in the Zynq UltraScale+ MPSoC Register Reference (UG1087) [Ref 4]. See Additional Resources and Legal Notices for a list of helpful documents and online resources.