s_axis_tx_tuser - 4.4 English

UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156)
Document ID
PG156
Release Date
2023-11-24
Version
4.4 English

Table: Mapping between s_axis_rq_tuser and s_axis_tx_tuser shows the mapping between s_axis_rq_tuser from Requester Request interface and s_axis_tx_tuser signal bus from the AXI4-Stream (Basic) Transmit interface.

Table A-16: Mapping between s_axis_rq_tuser and s_axis_tx_tuser

AXI4-Stream (Basic) Receive Interface Name

Mnemonic

AXI4-Stream (Enhanced) Requester Request Interface Name

Mnemonic

Comments

s_axis_tx_tuser[0]

tx_ecrc_gen

s_axis_rq_tdata[127]

Force ECRC

Same Functionality

s_axis_tx_tuser[1]

tx_err_fwd

s_axis_rq_tdata[79]

Poisoned request

Same

Functionality

s_axis_tx_tuser[2]

tx_str

NA

NA

No Equivalent Signal

s_axis_tx_tuser[2]

t_src_dsc

s_axis_rq_tuser[11]

Discontinue

Same

Functionality