The timing diagrams in This Figure , This Figure , and This Figure illustrate the Dword-aligned transfer of a memory write TLP received from the link across the Completer reQuest (CQ) interface, when the interface width is configured as 64, 128, and 256 bits, respectively. For illustration purposes, the starting Dword address of the data block being written into memory is assumed to be ( m × 32 + 1), for an integer m > 0. Its size is assumed to be n Dwords, for some n = k × 32 + 29, k > 0.
In both Dword-aligned and address-aligned modes, the transfer starts with the 16 descriptor bytes, followed immediately by the payload bytes. The m_axis_cq_tvalid signal remains asserted over the duration of the packet. You can prolong a beat at any time by deasserting m_axis_cq_tready . The AXI4-Stream interface signals s_axis_cq_tkeep (one per Dword position) indicate the valid Dwords in the packet including the descriptor and any null bytes inserted between the descriptor and the payload. That is, the tkeep bits are set to 1 contiguously from the first Dword of the descriptor until the last Dword of the payload. During the transfer of a packet, the tkeep bits can be 0 only in the last beat of the packet, when the packet does not fill the entire width of the interface. The m_axis_cq_tlast signal is always asserted in the last beat of the packet.
The CQ interface also includes the First Byte Enable and the Last Enable bits in the m_axis_cq_tuser bus. These are valid in the first beat of the packet, and specify the valid bytes of the first and last Dwords of payload.
The m_axi_cq_tuser bus also provides several informational signals that can be used to simplify the logic associated with the user interface, or to support additional features. The sop signal is asserted in the first beat of every packet, when its descriptor is on the bus. The byte enable outputs byte_en[31:0] (one per byte lane) indicate the valid bytes in the payload. The bits of byte_en are asserted only when a valid payload byte is in the corresponding lane (that is, not asserted for descriptor or padding bytes between the descriptor and payload). The asserted byte enable bits are always contiguous from the start of the payload, except when the payload size is two Dwords or less. For cases of one-Dword and two-Dword writes, the byte enables can be non-contiguous. Another special case is that of a zero-length memory write, when the integrated block transfers a one-Dword payload with all byte_en bits set to 0. Thus, in all cases the user logic can use the byte_en signals directly to enable the writing of the associated bytes into memory.
In the Dword-aligned mode, there can be a gap of zero, one, two, or three byte positions between the end of the descriptor and the first payload byte, based on the address of the first valid byte of the payload. The actual position of the first valid byte in the payload can be determined either from first_be[3:0] or byte_en[31:0] in the m_axis_cq_tuser bus.
When a Transaction Processing Hint is present in the received TLP, the integrated block transfers the parameters associated with the hint (TPH Steering Tag and Steering Tag Type) on signals within the m_axis_cq_tuser bus.
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The timing diagrams in This Figure , This Figure , and This Figure illustrate the address-aligned transfer of a memory write TLP received from the link across the CQ interface, when the interface width is configured as 64, 128 and 256 bits, respectively. For the purpose of illustration, the starting Dword address of the data block being written into memory is assumed to be ( m × 32 + 1), for an integer m > 0. Its size is assumed to be n Dwords, for some n = k × 32 + 29, k > 0.
In the address-aligned mode, the delivery of the payload always starts in the beat following the last byte of the descriptor. The first byte of the payload can appear on any byte lane, based on the address of the first valid byte of the payload. The keep outputs m_axis_cq_tkeep remain active-High in the gap between the descriptor and the payload. The actual position of the first valid byte in the payload can be determined either from the least significant bits of the address in the descriptor or from the byte enable bits byte_en[31:0] in the m_axis_cq_tuser bus.
For writes of two Dwords or less, the 1s on byte_en cannot be contiguous from the start of the payload. In the case of a zero-length memory write, the integrated block transfers a one-Dword payload with the byte_en bits all set to 0 for the payload bytes.
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