Table: PIO Design File Structure defines the PIO design file structure. Based on the specific core targeted, not all files delivered by the Vivado IP catalog are necessary, and some files might not be delivered. The major difference is that some of the Endpoint for PCIe solutions use a 32-bit user datapath, others use a 64-bit datapath, and the PIO design works with both. The width of the datapath depends on the specific core being targeted.
Three configurations of the PIO design are provided: PIO_64, PIO_128, and PIO_256 with 64-, 128-, and 256-bit AXI4-Stream interfaces, respectively. The PIO configuration that is generated depends on the selected Endpoint type (that is, UltraScale™ device integrated block, PIPE, PCI Express, and Block Plus) as well as the number of PCI Express lanes and the interface width selected. Table: PIO Configuration identifies the PIO configuration generated based on your selection.
Core |
x1 |
x2 |
x4 |
x8 |
---|---|---|---|---|
Integrated Block for PCIe |
PIO_64 |
PIO_64, PIO_128 |
PIO_64, PIO_128, PIO_256 |
PIO_64, PIO_128 (1) , PIO_256 |
Notes: 1. The core does not support 128-bit x8 8.0 Gb/s configuration and 500 MHz user clock frequency. |
This Figure shows the various components of the PIO design, which is separated into four main parts: the TX Engine, RX Engine, Memory Access Controller, and Power Management Turn-Off Controller.