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Port
|
Direction
|
Width
|
Description
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cfg_hot_reset_in
|
Input
|
1
|
Configuration Hot Reset In
In RP mode, assertion transitions LTSSM to hot reset state, active-High.
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cfg_hot_reset_out
|
Output
|
1
|
Configuration Hot Reset Out
In EP mode, assertion indicates that EP has transitioned to the hot reset state, active-High.
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cfg_config_space_enable
|
Input
|
1
|
Configuration Configuration Space Enable
When this input is set to 0 in the Endpoint mode, the core generates a CRS Completion in response to Configuration Requests. This port should be held deasserted when the core configuration registers are loaded from the DRP due to a change in attributes. This prevents the core from responding to Configuration Requests before all the registers are loaded. This input can be High when the power-on default values of the Configuration registers do not need to be modified before Configuration space enumeration. This input is not applicable for Root Port mode.
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cfg_per_function_update_done
|
Output
|
1
|
Configuration per Function Update Complete
Asserted in response to cfg_per_function_output_request assertion, for one cycle after the request is complete.
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cfg_per_function_number
|
Input
|
4
|
Configuration Per Function Target Function Number
The user provides the function number (0-7), where value 0–1 corresponds to PF0–1, and value 2–7 corresponds to VF0–5, and asserts cfg_per_function_output_request to obtain per function output values for the selected function. All other values are reserved
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cfg_per_function_output_request
|
Input
|
1
|
Configuration Per Function Output Request
When this port is asserted with a function number value on cfg_per_function_number, the core presents information on per-function configuration output pins and asserts cfg_update_done when complete.
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cfg_dsn
|
Input
|
64
|
Configuration Device Serial Number
Indicates the value that should be transferred to the Device Serial Number Capability on PF0. Bits [31:0] are transferred to the first (Lower) Dword (byte offset
0x4h
of the Capability), and bits [63:32] are transferred to the second (Upper) Dword (byte offset 0x8h of the Capability). After the user logic updates cfg_dsn port, the new cfg_dsn port should appear on the Extended Configuration Space. No additional qualifying control signal is required.
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cfg_ds_bus_number
|
Input
|
8
|
Configuration Downstream Bus Number
•
Downstream Port: Provides the bus number portion of the Requester ID (RID) of the Downstream Port. This is used in TLPs generated inside the core, such as UR Completions and Power-management messages; it does not affect TLPs presented on the AXI interface.
•
Upstream Port: No role.
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cfg_ds_port_number
|
Input
|
8
|
Configuration Downstream Port Number
Provides the port number field in the Link Capabilities register.
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|
cfg_ds_device_number
|
Input
|
5
|
Configuration Downstream Device Number
•
Downstream Port: Provides the device number portion of the RID of the Downstream Port. This is used in TLPs generated inside the core, such as UR Completions and Power-management messages; it does not affect TLPs presented on the TRN interface.
•
Upstream Port: No role.
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cfg_ds_function_number
|
Input
|
3
|
Configuration Downstream Function Number
•
Downstream Port: Provides the function number portion of the RID of the Downstream Port. This is used in TLPs generated inside the core, such as UR Completions and power-management messages; it does not affect TLPs presented on the TRN interface.
•
Upstream Port: No role.
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|
cfg_power_state_change_ack
|
Input
|
1
|
Configuration Power State Ack
You must assert this input to the core for one cycle in response to the assertion of cfg_power_state_change_interrupt, when it is ready to transition to the low-power state requested by the configuration write request. The user application can permanently hold this input High if it does not need to delay the return of the completions for the configuration write transactions, causing power-state changes.
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cfg_power_state_change_interrupt
|
Output
|
1
|
Power State Change Interrupt
The core asserts this output when the power state of a physical or virtual function is being changed to the D1 or D3 states by a write into its Power Management Control register. The core holds this output High until the user application asserts the cfg_power_state_change_ack input to the core. While cfg_power_state_change_interrupt remains High, the core does not return completions for any pending configuration read or write transaction received by the core. The purpose is to delay the completion for the configuration write transaction that caused the state change until the user application is ready to transition to the low-power state. When cfg_power_state_change_interrupt is asserted, the function number associated with the configuration write transaction is provided on the cfg_ext_function_number[7:0] output. When the user application asserts cfg_power_state_change_ack, the new state of the function that underwent the state change is reflected on cfg_function_power_state (for PFs) or the cfg_vf_power_state (for VFs) outputs of the core.
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cfg_subsys_id
|
Input
|
16
|
Configuration Subsystem ID
Indicates the value that should be transferred to the Type 0 PCI Capability Strucute Subsytem ID field on PF0.
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cfg_err_cor_in
|
Input
|
1
|
Correctable Error Detected
The user application activates this input for one cycle to indicate a correctable error detected within the user logic that needs to be reported as an internal error through the PCI Express Advanced Error Reporting (AER) mechanism. In response, the core sets the Corrected Internal Error Status bit in the AER Correctable Error Status register of all enabled functions, and also sends an error message if enabled to do so. This error is not considered function-specific.
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cfg_err_uncor_in
|
Input
|
1
|
Uncorrectable Error Detected
The user application activates this input for one cycle to indicate a uncorrectable error detected within the user logic that needs to be reported as an internal error through the PCI Express Advanced Error Reporting mechanism. In response, the core sets the uncorrected Internal Error Status bit in the AER Uncorrectable Error Status register of all enabled functions, and also sends an error message if enabled to do so. This error is not considered function-specific.
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cfg_flr_done
|
Input
|
4
|
Function Level Reset Complete
The user application must assert this input when it has completed the reset operation of the Virtual Function. This causes the core to deassert cfg_flr_in_process for physical function
i
and to re-enable configuration accesses to the physical function. Bits [3:2] are reserved.
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cfg_vf_flr_done
|
Input
|
8
|
Function Level Reset for Virtual Function is Complete
The user application must assert this input when it has completed the reset operation of the Virtual Function. This causes the core to deassert cfg_vf_flr_in_process for function
i
and to re-enable configuration accesses to the virtual function. Bits [7:6] are reserved.
|
|
cfg_flr_in_process
|
Output
|
4
|
Function Level Reset In Process
The core asserts bit
i
of this bus when the host initiates a reset of physical function
i
through its FLR bit in the configuration space. The core continues to hold the output High until the user sets the corresponding cfg_flr_done input for the corresponding physical function to indicate the completion of the reset operation. Bits [3:2] are reserved.
|
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cfg_vf_flr_in_process
|
Output
|
8
|
Function Level Reset In Process for Virtual Function
The core asserts bit
i
of this bus when the host initiates a reset of virtual function
i
though its FLR bit in the configuration space. The core continues to hold the output High until the user sets the corresponding cfg_vf_flr_done input for the corresponding function to indicate the completion of the reset operation.
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cfg_req_pm_transition_l23_ready
|
Input
|
1
|
When the core is configured as an Endpoint, the user application asserts this input to transition the power management state of the core to L23_READY (see Chapter 5 of the
PCI Express Specification
for a detailed description of power management). This is done after the PCI functions in the core are placed in the D3 state and after the user application acknowledges the PME_Turn_Off message from the Root Complex. Asserting this input causes the link to transition to the L3 state, and requires a hard reset to resume operation. This input can be hardwired to 0 if the link is not required to transition to L3. This input is not used in Root Complex mode.
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|
cfg_link_training_enable
|
Input
|
1
|
This input must be set to 1 to enable the Link Training Status State Machine (LTSSM) to bring up the link. Setting it to 0 forces the LTSSM to stay in the Detect.Quiet state.
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cfg_local_error
|
Output
|
1
|
Local Error Conditions
Output is logic High when any of the local error conditions listed in the Local Error Status Register occur. Each of the conditions can be selectively masked by setting the corresponding bits in the Local Interrupt Mask Register. Up to eight of the following back to back block internal events (if not masked) are reported.
1) tx_replay_buffer_ram_uncorrectable_parity_error
2) rx_request_fifo_ram_uncorrectable_parity_error
3) rx_completion_fifo_ram_uncorrectable_parity_error
4) rx_receive_fifo_overflow
5) rx_completion_receive_fifo_overflow
6) link_replay_timeout
7) link_replay_num_rollover
8) phy_error_detected
9) malformed_tlp_received_reg
10) unexpected_completion_received
11) flow_control_protocol_error_detected
12) completion_timeout
Note:
This signal may not work for all PCIe Link Width/Speed configurations. Do not rely solely on this signal to indicate an error.
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