With each PCI Express core generated from the Vivado IDE, AMD provides recommended locations of the GTH for the specified PCI Express block. While you can change the GTH locations, AMD cannot guarantee that timing closure will be possible with these alternative locations.
Starting with the Vivado 2014.3 software release, you have more flexibility to choose the GT locations used in a design. You can choose:
• The PCIe block and GTH quad location in which lane 0 is placed.
• The location of the GT quad, which can be one clock region above the PCIe block, in the same region as the PCIe block, or one clock region below the PCIe block.
After the quad location is chosen, the remaining GTH locations are constrained based on the link width selected. Note that SLR boundaries and non-bonded out GTs affect which GTHs are available. When a x8 link width is selected, both GTH quads used must be adjacent to each other.
This Figure show how lanes are distributed for each initial GTH quad locations for a x8 PCIe link width.
