Lane Reversal - 4.4 English

UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156)

Document ID
PG156
Release Date
2023-11-24
Version
4.4 English

The integrated block supports limited lane reversal capabilities and therefore provides flexibility in the design of the board for the link partner. The link partner can choose to lay out the board with reversed lane numbers and the integrated block continues to link train successfully and operate normally. The configurations that have lane reversal support are x8 and x4 (excluding downshift modes). Downshift refers to the link width negotiation process that occurs when link partners have different lane width capabilities advertised. As a result of lane width negotiation, the link partners negotiate down to the smaller of the advertised lane widths. Table: Lane Reversal Support describes the several possible combinations including downshift modes and availability of lane reversal support.

Table 3-19: Lane Reversal Support

Integrated Block
Advertised
Lane Width

Negotiated
Lane
Width

Lane Number Mapping
(Endpoint Link Partner)

Lane
Reversal
Supported

Endpoint

Link Partner

x8

x8

Lane 0... Lane 7

Lane 7... Lane 0

Yes

x8

x4

Lane 0... Lane 3

Lane 7... Lane 4

No (1)

x8

x2

Lane 0... Lane 3

Lane 7... Lane 6

No (1)

x4

x4

Lane 0... Lane 3

Lane 3... Lane 0

Yes

x4

x2

Lane 0... Lane 1

Lane 3... Lane 2

No (1)

x2

x2

Lane 0... Lane 1

Lane 1... Lane 0

Yes

x2

x1

Lane 0... Lane 1

Lane 1

No (1)

Notes:

1. When the lanes are reversed in the board layout and a downshift adapter card is inserted between the Endpoint and link partner, Lane 0 of the link partner remains unconnected (as shown by the lane mapping in this table) and therefore does not link train.