The PCI Express Base Specification [Ref 2] requires that the Completer Request interface continue to deliver Posted transactions even when the user application is unable to accept Non-Posted transactions. To enable this capability, the integrated block implements a credit-based flow control mechanism on the CQ interface through which user logic can control the flow of Non-Posted requests without affecting Posted requests. The user logic signals the availability of buffers for receive Non-Posted requests using the pcie_cq_np_req[0] signal. The core delivers a Non-Posted request only when the available credit is non-zero. The integrated block continues to deliver Posted requests while the delivery of Non-Posted requests has been paused for lack of credit. When no back pressure is applied by the credit mechanism for the delivery of Non-Posted requests, the integrated block delivers Posted and Non-Posted requests in the same order as received from the link.
The integrated block maintains an internal credit counter to track the credit available for Non-Posted requests on the completer request interface. The following algorithm is used to keep track of the available credit:
• On reset, the counter is set to 0.
• After the integrated block comes out of reset, in every clock cycle:
° If pcie_cq_np_req[0] is active-High and no Non-Posted request is being delivered this cycle, the credit count is incremented by 1, unless it has already reached its saturation limit of 32.
° If pcie_cq_np_req[0] is Low and a Non-Posted request is being delivered this cycle, the credit count is decremented by 1, unless it is already 0.
° Otherwise, the credit count remains unchanged.
• The integrated block starts delivery of a Non-Posted TLP only if the credit count is greater than 0.
The user application can either provide a one-cycle pulse on pcie_cq_np_req[0] each time it is ready to receive a Non-Posted request, or keep it permanently asserted if it does not need to exercise selective back pressure of Non-Posted requests. If the credit count is always non-zero, the integrated block delivers Posted and Non-Posted requests in the same order as received from the link. If it remains 0 for some time, Non-Posted requests can accumulate in the integrated block FIFO. When the credit count becomes non-zero later, the integrated block first delivers the accumulated Non-Posted requests that arrived before Posted requests already delivered, and then reverts to delivering the requests in the order received from the link.
The assertion and deassertion of the pcie_cq_np_req[0] signal does not need to be aligned with the packet transfers on the completer request interface.
You can monitor the current value of the credit count on the output pcie_cq_np_req _ count[5:0] . The counter saturates at 32. Because of internal pipeline delays, there can be several cycles of delay between the integrated block receiving a pulse on the pcie_cq_np_req[0] input and updating the pcie_cq_np_req_count[5:0] output in response. Thus, when the user application has adequate buffer space available, it should provide the credit in advance so that Non-Posted requests are not held up by the core for lack of credit.