Summary - 4.4 English

UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156)

Document ID
PG156
Release Date
2023-11-24
Version
4.4 English

The Configurator example design is a synthesizable design that demonstrates the capabilities of the UltraScale Devices Gen3 Integrated Block for PCIe when configured as a Root Port. The example is provided through the Vivado IDE and uses the Endpoint PIO example as a target for PCI Express enumeration and configuration. The design can be modified to target other Endpoints by changing the contents of a ROM file.