On the transmit side, the integrated block receives TLPs on
two different interfaces: the Requester reQuest (RQ) interface and the Completer Completion
(CC) interface. The integrated block does not reorder transactions received from each of these
interfaces. It is difficult to predict how the requester-side requests and completer-side
completions are ordered in the transmit pipeline of the integrated block, after these have
been multiplexed into a single traffic stream. In cases where completion TLPs must maintain
ordering with respect to requests, user logic can supply a 4-bit sequence number with any
request that needs to maintain strict ordering with respect to a Completion transmitted from
the CC interface, on the seq_num[3:0] inputs within the
s_axis_rq_tuser bus. The integrated block places this sequence number on
its pcie_rq_seq_num[3:0] output and asserts
pcie_rq_seq_num_vld when the request TLP has reached a point in the
transmit pipeline at which no new completion TLP from the user application can pass it. This
mechanism can be used in the following situations to maintain TLP order:
- The user logic requires ordering to be maintained
between a request TLP and a completion TLP that follows it. In this case, user logic must
wait for the sequence number of the requester request to appear on the
pcie_rq_seq_num[3:0]output before starting the transfer of the completion TLP on the target completion interface. - The user logic requires ordering to be maintained
between a request TLP and MSI/MSI-X TLP signaled through the MSI Message interface. In this
case, the user logic must wait for the sequence number of the requester request to appear on
the
pcie_rq_seq_num[3:0]output before signaling MSI or MSI-X on the MSI Message interface.