First, for both variations, the floorplan is established as part of the IP creation and should not be modified, but Tandem with Field Updates creates two sets of Pblocks instead of one. In addition to the same Pblocks tagged with HD.TANDEM for the stage 1 logic, a second, much larger set of Pblocks tagged with HD.RECONFIGURABLE for the user application are inferred. The former applies the same stage 1 creation rules as the standard Tandem Configuration solution. The latter enforces all rules for Dynamic Function eXchange, most notably routing containment to ensure the partial bitstream contains the entirety of the implementation for the user application.
The following figure shows the floorplan generated for the KU040 sample design for Tandem with Field Updates. The pink region is reserved for the UltraScale Devices Gen3 Integrated Block for PCIe core. This region includes the PCIe hard block, CLB, block RAM and transceiver sites for implementing the IP, and one I/O bank to enable the physical reset pin. The yellow region is the inverse of the pink and represents the Reconfigurable Partition (RP) for the user application. It covers remaining resources including all clocks, transceivers, I/O and logic not covered by the PCIe IP.
update_region), you can find the PIO example design logic, as well as the
collection of partition pins used to connect the two sections of the design.For more information on partition pins or other aspects of the Dynamic Function eXchange solution, see the Vivado Design Suite User Guide: Dynamic Function eXchange (UG909).