Bitstream configuration times can also be affected by:
• Power supply ramp times, including any delays due to regulators
• T POR (power on reset)
Power-supply ramp times are design-dependent. Take care to not design in large ramp times or delays. The FPGA power supplies that must be provided to begin FPGA configuration are listed in UltraScale Architecture Configuration User Guide (UG570) [Ref 7] .
In many cases, the FPGA power supplies can ramp up simultaneously or even slightly before the system power supply. In these cases, the design gains timing margin because the 100 ms does not start counting until the system supplies are stable. Again, this is design-dependent. Systems should be characterized to determine the relationship between FPGA supplies and system supplies.
T POR is 57 ms for standard power ramp rates, and 20 ms for fast ramp rates for UltraScale devices. See Kintex UltraScale Architecture Data Sheet: DC and AC Switching Characteristics (DS892) [Ref 8] , and Virtex UltraScale Architecture Data Sheet: DC and AC Switching Characteristics (DS893) [Ref 9] .
Consider two cases for Example 1 (Quad SPI flash [x4] operating at 66 MHz ± 200 ppm) from Calculating Bitstream Load Time for Tandem :
Assume that the FPGA power supplies ramp to a stable level (2 ms) after the 3.3V and 12V system power supplies. This time difference is called T FPGA_PWR . In this case, because the FPGA supplies ramp after the system supplies, the power supply ramp time takes away from the 100 ms margin.
The equations to test are:
T POR + Bitstream Load Time + T FPGA_PWR < 100 ms for non-ATX
T POR + Bitstream Load Time + T FPGA_PWR - 100 ms < 100 ms for ATX