Configuration Management Interface - 4.4 English - PG156

The ports used by configuration registers are described in Configuration Status Interface. Root Ports must use the Configuration Port to set up the Configuration Space. Endpoints can also use the Configuration Port to read and write; however, care must be taken to avoid adverse system side effects.

The user application must supply the address as a Dword address, not a byte address.

For example:

For the Command/Status register in the PCI Configuration Space Header:

• The Dword address of is 01h.
  Note: The byte address is 04h.

For BAR0:

• The Dword address is 04h.
  Note: The byte address is 10h.

To read any register in configuration space, the user application drives the register Dword address onto cfg_mgmt_addr[9:0]. cfg_mgmt_addr[17:10] selects the PCI Function associated with the configuration register. The core drives the content of the addressed register onto ^{cfg_mgmt_read_data[31:0]}. The value on cfg_mgmt_read_data[31:0] is qualified by signal assertion on cfg_mgmt_read_write_done. The following figure illustrates an example with read from the Configuration Space.

To write any register in configuration space, the user logic places the address on cfg_mgmt_addr bus, write data on cfg_mgmt_write_data , byte-valid on cfg_mgmt_byte_enable [3:0], and asserts the cfg_mgmt_write signal. In response, the core asserts the cfg_mgmt_read_write_done signal when the write is complete (which can take several cycles). The user logic must keep cfg_mgmt_addr, cfg_mgmt_write_data, cfg_mgmt_byte_enable and c fg_mgmt_write stable until cfg_mgmt_read_write_done is asserted. The user logic must also deassert cfg_mgmt_write in the cycle following the cfg_mgmt_read_write_done from the core.

When the core is configured in the Root Port mode, when you assert ^{cfg_mgmt_type1_cfg_reg_access} input during a write to a Type-1 PCI™ Configuration register forces a write into certain read-only fields of the register.