Integrated Block Endpoint Configuration Overview - 4.4 English - PG156

UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156)

Document ID
PG156
Release Date
2024-12-06
Version
4.4 English

The example simulation design for the Endpoint configuration of the integrated block consists of two discrete parts:

  • The Root Port Model, a test bench that generates, consumes, and checks PCI Express® bus traffic.
  • The Programmed Input/Output (PIO) example design, a completer application for PCI Express. The PIO example design responds to Read and Write requests to its memory space and can be synthesized for testing in hardware.