The following table describes the tests provided with the Root Port Model, followed by specific sections for Verilog test selection.
| Test Name | Test in Verilog | Description |
|---|---|---|
| sample_smoke_test0 | Verilog | Issues a PCI Type 0 Configuration Read TLP and waits for the completion TLP; then compares the value returned with the expected Device/Vendor ID value. |
| sample_smoke_test1 | Verilog | Performs the same operation as sample_smoke_test0 but makes use of expectation tasks. This test uses two separate test program threads: one thread issues the PCI Type 0 Configuration Read TLP and the second thread issues the Completion with Data TLP expectation task. This test illustrates the form for a parallel test that uses expectation tasks. This test form allows for confirming reception of any TLPs from your design. Additionally, this method can be used to confirm reception of TLPs when ordering is unimportant. |