This section demonstrates the Vivado tool flow from start to finish when targeting the VCU108 reference board . Paths and pointers within this flow description assume the default component name “pcie3_ultrascale_0” is used.
1. Create a new Vivado project , and selec t a supported p a r t/pa c kage s hown in Table: Tandem PROM/PCIe Supported Configurations .
2. In the Vivado IP catalog, expand Standard Bus Interfaces > PCI Express , and double-click UltraScale FPGA Gen3 Integrated Block for PCI Express to open the Customize IP dialog box.
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X-Ref Target - Figure 3-6 
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3. In the Customize IP dialog box Basic tab, ensure the following options are selected:
° Mode: Advanced
° PCIe Block Location: X0Y0
Note: Use the required PCIe Block Location for the device targeted, as listed in Table: Tandem PROM/PCIe Supported Configurations .
° Tandem Configuration or Dynamic Function eXchange: Tandem
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X-Ref Target - Figure 3-7 
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4. Perform additional PCIe customizations, and click OK to generate the core.
5. Click Generate when asked about which Output Products to create.
6. In the Sources tab, right-click the core, and select Open IP Example Design .
A new instance of Vivado is created and the example design is automatically loaded into the Vivado IDE.
7. Run Synthesis and Implementation.
Click Run Implementation in the Flow Navigator. Select OK to run through synthesis first. The design runs through the complete tool flow and the result is a fully routed design that supports Tandem PROM.
8. Setup PROM or Flash settings.
Set the appropriate settings to correctly generate a bitstream for a PROM or flash memory device. In the PCIe core constraint file (e.g. xilinx_pcie3_uscale_ep_x8g3.xdc ):
° Uncomment and customize any constraints that define the configuration settings.
°
The one constraint that is required is CONFIG_MODE. For example:
set_property CONFIG_MODE BPI16 [current_design]
For more information, see Programming the Device .
9. Generate the bitstream.
After Synthesis and Implementation is complete, click Generate Bitstream in the Flow Navigator. A bitstream supporting Tandem configuration is generated in the runs directory, for example: ./pcie_ultrascale_0_example.runs/impl/xilinx_pcie 3 _uscale_ep.bit .
Note: You have the option of creating the first and stage 2 bitstreams independently. This flow allows you to control the loading of each stage through the JTAG interface for testing purposes. These bitstreams are the same as the ones used for the Tandem PCIe solution when loaded using JTAG. Attempting to load only the stage1 bitstream from flash memory does not work in hardware due to the difference in the HD.OVERRIDE_PERSIST setting that is used for Tandem PCIe designs.
set_property HD.TANDEM_BITSTREAMS SEPARATE [current_design]
The resulting bit files created are named xilinx_pcie 3 _uscale_ep_tandem1.bit and xilinx_pcie 3 _uscale_ep_tandem2.bit .
10. Generate the PROM file.
Run the following command in the Vivado Tcl Console to create a PROM file supported on the VCU108 development board.
write_cfgmem -format mcs -interface BPI -size 256 -loadbit “up 0x0 xilinx_pcie 3 _uscale_ep.bit” xilinx_pcie3_uscale_ep.mcs