Table: Configuration Attributes of the Integrated Block User Interface lists the configuration attributes controlling the operation of the user interface of the core.
|
Attribute Name |
Type |
Description |
|---|---|---|
|
USER_CLK2_FREQ |
Integer |
• 2: 62.50 MHz (default) • 3: 125.00 MHz • 4: 250.00 MHz |
|
PL_LINK_CAP_MAX_LINK_SPEED[2:0] |
Bit vector |
Defines the maximum speed of the PCIe link. • 001: 2.5 GT/s • 010: 5.0 GT/s • 100: 8.0 GT/s All other encodings are reserved. |
|
PL_LINK_CAP_MAX_LINK_WIDTH[3:0] |
Bit vector |
Maximum Link Width. Valid settings are: • 0001b: x1 • 0010b: x2 • 0100b: x4 • 1000b: x8 All other encodings are reserved. This setting is propagated to all layers in the core. |
|
C_DATA_WIDTH |
Integer |
Configures the width of the AXI4-Stream interfaces. • 64 bit interface • 128 bit interface • 256 bit interface |
|
AXISTEN_IF_CQ_ALIGNMENT_MODE |
String |
Defines the data alignment mode for the completer request interface. • FALSE: Dword-aligned Mode • TRUE: Address-aligned Mode |
|
AXISTEN_IF_CC_ALIGNMENT_MODE |
String |
Defines the data alignment mode for the completer completion interface. • FALSE: Dword-aligned Mode • TRUE: Address-aligned Mode |
|
AXISTEN_IF_RQ_ALIGNMENT_MODE |
String |
Defines the data alignment mode for the requester request interface. • FALSE: Dword-aligned Mode • TRUE: Address-aligned Mode |
|
AXISTEN_IF_RC_ALIGNMENT_MODE |
String |
Defines the data alignment mode for the requester completion interface. • FALSE: Dword-aligned Mode • TRUE: Address-aligned Mode |
|
AXISTEN_IF_RC_STRADDLE |
String |
This attribute enables the straddle option on the requester completion interface. • FALSE: Straddle option disabled • TRUE: Straddle option enabled |
|
AXISTEN_IF_RQ_PARITY_CHECK |
String |
This attribute enables parity checking on the requester request interface. • FALSE: Parity check disabled • TRUE: Parity check enabled |
|
AXISTEN_IF_CC_PARITY_CHECK |
String |
This attribute enables parity checking on the completer completion interface. • FALSE: Parity check disabled • TRUE: Parity check enabled |
|
AXISTEN_IF_ENABLE_RX_MSG_INTFC |
String |
This attribute controls how the core delivers a message received from the link. When this attribute is set to FALSE, the core delivers the received message TLPs on the completer request interface using the AXI4-Stream protocol. In this mode, you can select the message types to receive using the AXISTEN_IF_ENABLE_MSG_ROUTE attributes. The receive message interface is inactive in this mode. When this attribute is set to TRUE, the core internally decodes messages received from the link, and signals them to the user by activating the cfg_msg_received signal on the receive message interface. The core does not transfer any message TLPs on the completer request interface. The settings of the AXISTEN_ENABLE_MSG_ROUTE attributes have no effect on the operation of the receive message interface in this mode. |
|
AXISTEN_IF_ENABLE_MSG_ROUTE[17:0] |
Bit vector |
When the AXISTEN_IF_ENABLE_RX_MSG_INTFC attribute is set to 0, you can use these attributes to select the specific message types you want to receive on the completer request interface. Setting a bit to 1 enables the delivery of the corresponding type of messages on the interface, and setting it to 0 results in the core filtering the message. Table: AXISTEN_IF_ENABLE_MSG_ROUTE Attribute Bit Descriptions defines the attribute bit definitions corresponding to the various message types. |
|
AXISTEN_IF_ENABLE_CLIENT_TAG |
String |
When set to FALSE, tag management for Non-Posted transactions initiated from the requester request interface is performed by the integrated block. That is, for each Non-Posted request, the core allocates the tag for the transaction and communicates it to the user interface. Setting set to TRUE, disables the internal tag management, allowing the user logic to supply the tag to be used for each request. The user logic must present the Tag field in the Request descriptor header in the range 0–31 when the PF0_DEV_CAP_EXT_TAG_SUPPORTED attribute is FALSE, while the Tag field can be in the range 0–63 when the PF0_DEV_CAP_EXT_TAG_SUPPORTED attribute is TRUE. |