Device Utilization - 4.4 English - PG156

UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156)
Document ID
PG156
Release Date
2024-12-06
Version
4.4 English

The following table shows the PIO design FPGA resource utilization.

Table 1. PIO Design FPGA Resources
Resources Utilization
LUTs 300
Flip-Flops 500
Block RAMs 4