Number of Lanes - 4.4 English

UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156)

Document ID
PG156
Release Date
2023-11-24
Version
4.4 English

The core requires the selection of the initial lane width. See Table: Lane Width and Product Generated defines the available widths and associated generated core. Wider lane width cores can train down to smaller lane widths if attached to a smaller lane-width device. See Link Training: 2-Lane, 4-Lane, and 8-Lane Components for more information.

Table 4-1: Lane Width and Product Generated

Lane Width

Product Generated

x8

8-Lane UltraScale FPGA Gen3 Integrated Block for PCI Express