The core requires the selection of the initial lane width. The following table defines the available widths and associated generated core. Wider lane width cores can train down to smaller lane widths if attached to a smaller lane-width device. See Link Training: 2-Lane, 4-Lane, and 8-Lane Components for more information.
Lane Width | Product Generated |
---|---|
x8 | 8-Lane UltraScale FPGA Gen3 Integrated Block for PCI Express |