Fundamental to the operation of the core, the Clock and Reset interface provides the system-level clock and reset to the core as well as the user application clock and reset signal. Table: Clock and Reset Interface Port Descriptions defines the ports in the Clock and Reset interface of the core.
Note: The phy ready indication signal, phy_rdy_out , indicates that the GT Wizard is ready. This signal is driven by phy_rst FSM on receiving the phy status from the GT Wizard core.
|
Port |
Direction |
Width |
Description |
|---|---|---|---|
|
user_clk |
Output |
1 |
User clock output (62.5, 125, or 250 MHz) This clock has a fixed frequency and is configured in the Vivado™ Integrated Design Environment (IDE). |
|
user_reset |
Output |
1 |
This signal is deasserted synchronously with respect to user_clk. It is deasserted and asserted asynchronously with sys_reset assertion. |
|
sys_clk |
Input |
1 |
Reference clock This clock has a selectable frequency of 100 MHz, 125 MHz, or 250 MHz. |
|
sys_clk_gt |
Input |
1 |
PCIe reference clock for GT. This clock must be driven directly from IBUFDS_GTE3 (same definition and frequency as sys_clk). This clock has a selectable frequency of 100 MHz, 125 MHz, or 250 MHz, which is the same as in sys_clk. |
|
sys_reset |
Input |
1 |
Fundamental reset input to the core (asynchronous) This input is active-Low by default to match the PCIe edge connector reset polarity. You can reset to active-High using an option in the Vivado IDE, but this can result in incompatibility with the PCIe edge connector. Dedicated routing between the FPGA PERSTN0 package pin and the PCIe integrated block is enabled by default where available. Table: Tandem PROM/PCIe Supported Configurations identifies the PCIe sites and their corresponding dedicated sys_reset IOB location. No other PCIe integrated block locations have dedicated sys_reset connections. Use the dedicated routing and the associated IOB when possible. To use another sys_reset pin location, the Use the dedicated PERST routing resources parameter must be disabled in the Vivado IDE. In addition, use the PERSTN1 package pin for the sys_reset location of endpoint configurations for PCIe sites not listed in Table: Tandem PROM/PCIe Supported Configurations . |
|
pcie_perstn0_out |
Output |
1 |
Output that is a direct pass-through from the PERSTN0 package pin through the sys_reset input port for the PCIe site listed in Table: Tandem PROM/PCIe Supported Configurations . This port is only available when dedicated routing (through the Use the dedicated PERST routing resources parameter) is enabled (default), and sys_reset is driven by the PERSTN0 package pin. For all other configurations and PCIe locations, this port should not be connected. |
|
pcie_perstn1_in |
Input |
1 |
Input to a dedicated route from the PERSTN1 package pin to the pcie_perstn1_out output. This input can be driven only by the PERSTN1 package pin and should only be used when dedicated routing (through the Use the dedicated PERST routing resources parameter) is enabled (default). For PCIe locations that do not support dedicated reset routing, this port should be tied to a constant zero (1'b0). |
|
pcie_perstn1_out |
Output |
1 |
Output that is a direct pass-through from the PERSTN1 package pin through the pcie_perstn1_in input port for the PCIe integrated blocks that support dedicated routing. This port can only be used when dedicated reset routing (through the Use the dedicated PERST routing resources parameter) is enabled, and pcie_perstn1_in is driven by the PERSTN1 package pin. For all other configurations, this port should not be connected. Optionally, the PERSTN1 package pin can be used to drive the sys_reset input port for PCIe endpoint configurations that do not support dedicate reset routing. |
The PERSTN0 / PERSTN1 package pins and the reset input ports described in Table: Clock and Reset Interface Port Descriptions are used for dedicated PCIe reset routing. These are dedicated ports from the PERSTN package pins to specific PCIe integrated block locations. Users who need Tandem Configuration support should use these pins as described in Table: Clock and Reset Interface Port Descriptions . The general guidelines for using PERSTN0 and PERSTN1 pins are as follows:
• Root Port configurations can use any pin to drive the edge connector reset.
• Endpoint configurations should always use PERSTN0 as PCIe edge connector reset input pin if dedicated routing is available.
• Endpoint configurations should give priority to PERSTN1 as the PCIe edge connector reset input pin, if dedicated reset routing is not available, but can use any pin as desired.