Test Description - 4.4 English - PG156

UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156)

Document ID
PG156
Release Date
2024-12-06
Version
4.4 English

The Root Port Model provides a Test Program Interface (TPI). The TPI provides the means to create tests by invoking a series of Verilog tasks. All Root Port Model tests should follow the same six steps:

  1. Perform conditional comparison of a unique test name
  2. Set up master timeout in case simulation hangs
  3. Wait for Reset and link-up
  4. Initialize the configuration space of the Endpoint
  5. Transmit and receive TLPs between the Root Port Model and the Endpoint DUT
  6. Verify that the test succeeded