The Root Port Model provides a Test Program Interface (TPI). The TPI provides the means to create tests by invoking a series of Verilog tasks. All Root Port Model tests should follow the same six steps:
- Perform conditional comparison of a unique test name
- Set up master timeout in case simulation hangs
- Wait for Reset and link-up
- Initialize the configuration space of the Endpoint
- Transmit and receive TLPs between the Root Port Model and the Endpoint DUT
- Verify that the test succeeded