The final size of the stage 1 bitstream varies based on many factors, including:
• IP : The size and shape of the first-stage Pblocks determine the number of frames required for stage 1.
• Device : Wider devices require more routing frames to connect the IP to clocking resources.
• Design : Location of the reset pin is one of many factors introduced by the addition of the user application.
• GT Locations : The selection of the GT quads used affects the size of the stage 1 bitstream. For the most efficient use of resources, the GT quad adjacent to the PCI Express hard block should be used.
• Compression : As the device utilization increases, the effectiveness of compression decreases.
As a baseline, here are some sample bitstream sizes and configuration times for the example (PIO) design generated along with the PCIe IP.
|
Device |
Full Bitstream |
Full: BPI16
|
Tandem Stage 1 (2) |
Tandem: BPI16
|
|---|---|---|---|---|
|
KU040 |
122.1 Mb |
152.7 ms |
7.6 Mb |
9.5 ms |
|
VU095 |
273.5 Mb |
341.8 ms |
8.8 Mb |
10.9 ms |
|
VU190 |
577.1 Mb |
721.4 ms |
11.2 Mb |
14.1 ms |
|
Notes: 1. The configuration times shown here do not include T POR . 2. Because the PIO design is very small, compression is very effective in reducing the bitstream size. These numbers were obtained without compression to give a more accurate estimate of what a full design might show. These numbers were generated using a PCIe Gen3x8 configuration in Vivado Design Suite 2015.1. |
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The amount of time it takes to load the stage 2 bitstream using the Tandem PCIe methodology depends on three additional factors:
• The width and speed of PCI Express link.
• The frequency of the clock used to program the MCAP.
• The efficiency at which the Root Port host can deliver the bitstream to the Endpoint FPGA design. For most designs this is the limiting factor.
The lower bandwidth of these three factors determines how fast the stage 2 bitstream is loaded.