Because the functionality of the Tandem PROM or Tandem PCIe core relies on the STARTUP module, this must be taken into consideration during simulation.
The PCI Express core relies on the STARTUP block to assert the EOS output status signal in order to know when the stage 2 bitstream has been loaded into the device. You must simulate the STARTUP block behavior to release the PCIe core to work with the stage 2 logic. This is done using a hierarchical reference to force the EOS signal on the STARTUP block because result simulators, which do not support hierarchical reference, cannot be used to simulate Tandem designs. The following pseudo code shows how this could be done.
// Initialize EOS at time 0
force board.EP.pcie_ip_support_i.pcie_ip_i.inst.startup_i.EOS = 1'b1;
<delay until after PCIe reset is released>
// Deassert EOS to simulate the starting of the 2nd stage bitstream loading
force board.EP.pcie_ip_support_i.pcie_ip_i.inst.startup_i.EOS = 1'b0;
<delay a minimum of 4 user_clk cycles>
// Reassert EOS to simulate that 2nd stage bitstream completed loading
force board.EP.pcie_ip_support_i.pcie_ip_i.inst.startup_i.EOS = 1'b1;
// Simulate as normal from this point on.
The hierarchy to the PCIe core in the line above must be changed to match that of the user design. This line can also be found in the example simulation provided with the core in the file named board.v .